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"Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster ..."

Shashwat Shrivastava et al. (2023)

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DOI: 10.1145/3543622.3573161

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-07

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  - conf/fpga/ShrivastavaNRGS23
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  - https://dblp.org/rec/conf/fpga/ShrivastavaNRGS23
Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA 2023: 231

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