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ORCIDKing Ho Tam
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2010 – 2019
- 2015
[c9]Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang:
Criticality-dependency-aware timing characterization and analysis. DAC 2015: 167:1-167:6- 2014
- [c8]Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang:
Design and manufacturing process co-optimization in nano-technology. ICCAD 2014: 574-581
2000 – 2009
- 2008
- [j2]King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1498-1502 (2008) - [c7]Igor Keller, King Ho Tam, Vinod Kariat:
Challenges in gate level modeling for delay and SI at 65nm and below. DAC 2008: 468-473 - 2007
- [j1]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 845-857 (2007) - [c6]Yu Hu, King Ho Tam, Tong Jing, Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP 2007: 95-102 - 2005
- [c5]King Ho Tam, Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages. DAC 2005: 497-502 - [c4]Jinjun Xiong, King Ho Tam, Lei He:
Buffer Insertion Considering Process Variation. DATE 2005: 970-975 - [c3]Yu Ching Chang, King Ho Tam, Lei He:
Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ISLPED 2005: 137-142 - [c2]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD 2005: 78-85 - 2004
- [c1]Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He:
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. ISQED 2004: 69-74
Coauthor Index
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