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ORCIDDuncan G. Elliott
Person information
- affiliation: University of Alberta, Edmonton, Canada
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Journal Articles
- 2020
[j21]John Petrus Grey
, Ian R. Mann, Michael D. Fleischauer, Duncan G. Elliott:
Analytic Model for Low Earth Orbit Satellite Solar Power. IEEE Trans. Aerosp. Electron. Syst. 56(5): 3349-3359 (2020)- 2019
- [j20]Honglan Jiang, Leibo Liu, Pieter P. Jonker, Duncan G. Elliott, Fabrizio Lombardi, Jie Han:
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 313-326 (2019) - 2018
- [j19]Xiaoxue Jiang, Xiaojian Yu, Kambiz Moez, Duncan G. Elliott, Jie Chen:
High-Efficiency Charge Pumps for Low-Power On-Chip Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1143-1153 (2018) - 2016
- [j18]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Design, evaluation and fault-tolerance analysis of stochastic FIR filters. Microelectron. Reliab. 57: 111-127 (2016) - [j17]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3169-3183 (2016) - 2013
- [j16]Jinghang Liang, Zhiyin Zhou, Jie Han, Duncan G. Elliott:
A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 108-115 (2013) - 2012
- [j15]Philip A. Marshall, Vincent C. Gaudet, Duncan G. Elliott:
Deeply Pipelined Digit-Serial LDPC Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2934-2944 (2012) - 2011
- [j14]John C. Koob, Sue Ann Ung, Bruce F. Cockburn, Duncan G. Elliott:
Design and Characterization of a Multilevel DRAM. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1583-1596 (2011) - 2010
- [j13]Zhengang Chen, Tyler L. Brandon, Duncan G. Elliott, Stephen Bates, Witold A. Krzymien, Bruce F. Cockburn:
Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 836-849 (2010) - 2009
- [j12]Maziyar Khorasani, Mohammad Behnam, Leendert van den Berg, Christopher J. Backhouse, Duncan G. Elliott:
High-Voltage CMOS Controller for Microfluidics. IEEE Trans. Biomed. Circuits Syst. 3(2): 89-96 (2009) - [j11]Tyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott:
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 1017-1029 (2009) - 2008
- [j10]Tyler L. Brandon, Robert Hang, Gary Block, Vincent C. Gaudet, Bruce F. Cockburn, Sheryl L. Howard, Christian Giasson, Keith Boyle, Paul Goud, Siavash Sheikh Zeinoddin, Anthony Rapley, Stephen Bates, Duncan G. Elliott, Christian Schlegel:
A scalable LDPC decoder ASIC architecture with bit-serial message exchange. Integr. 41(3): 385-398 (2008) - [j9]Zhengang Chen, Tyler L. Brandon, Stephen Bates, Duncan G. Elliott, Bruce F. Cockburn:
Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3628-3640 (2008) - 2007
- [j8]Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon, Bruce F. Cockburn, Duncan G. Elliott, John C. Koob, Zhengang Chen:
Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder. IEEE J. Solid State Circuits 42(10): 2245-2256 (2007) - [j7]Raymond J. Sung, Duncan G. Elliott:
Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 460-464 (2007) - 2006
- [j6]Stephen Bates, Duncan G. Elliott, Ramkrishna Swamy:
Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1909-1917 (2006) - [j5]Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn:
Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2595-2605 (2006) - 2005
- [j4]John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath:
Design of a 3-D fully depleted SOI computational RAM. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 358-369 (2005) - 2003
- [j3]Kristopher C. Breen, Duncan G. Elliott:
Aliasing and anti-aliasing in branch history table prediction. SIGARCH Comput. Archit. News 31(5): 1-4 (2003) - 1999
- [j2]Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott:
Fault Models and Tests for a 2-Bit-per-Cell MLDRAM. IEEE Des. Test Comput. 16(1): 22-31 (1999) - [j1]Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie:
Computational RAM: Implementing Processors in Memory. IEEE Des. Test Comput. 16(1): 32-41 (1999)
Conference and Workshop Papers
- 2019
- [c21]Stefan Damkjar, Collin Cupido, Charles Nokes, Ian R. Mann, Duncan G. Elliott:
Design and Verification of a Robust Release Mechanism for CubeSat Deployables. CCECE 2019: 1-4 - 2018
- [c20]Jinghang Liang, Duncan G. Elliott:
Frequency Synthesis Based on A Novel Differential Locking Mechanism. ISCAS 2018: 1-5 - 2016
- [c19]Jinghang Liang, Duncan G. Elliott:
Coresidual alias-locked loops. ISCAS 2016: 9-12 - [c18]David L. Sloan, Benjamin Martin, Gordon Hall, Andrew Hakman, Philip A. Marshall, Stephane Martel, Christopher J. Backhouse, Vincent C. Gaudet, Duncan G. Elliott:
HV-CMOS single-chip electronics platform for lab-on-chip DNA analysis. ISCAS 2016: 2427-2430 - 2015
- [c17]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Stochastic circuit design and performance evaluation of vector quantization. ASAP 2015: 111-115 - [c16]Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott:
Design and evaluation of stochastic FIR filters. PACRIM 2015: 407-412 - 2012
- [c15]Philip A. Marshall, Vincent C. Gaudet, Duncan G. Elliott:
Effects of Varying Message Precision in Digit-Online LDPC Decoders. SiPS 2012: 7-12 - [c14]Si-Yun J. Li, Tyler L. Brandon, Duncan G. Elliott, Vincent C. Gaudet:
Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder. SiPS 2012: 294-299 - 2008
- [c13]Leendert van den Berg, Duncan G. Elliott:
An alias-locked loop frequency synthesis architecture. ISCAS 2008: 1536-1539 - [c12]Maziyar Khorasani, Leendert van den Berg, Philip A. Marshall, Meysam Zargham, Vincent C. Gaudet, Duncan G. Elliott, Stephane Martel:
Low-power static and dynamic high-voltage CMOS level-shifter circuits. ISCAS 2008: 1946-1949 - [c11]Tyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott:
A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. ISCAS 2008: 3090-3093 - 2006
- [c10]Zhengang Chen, Stephen Bates, Duncan G. Elliott, Tyler L. Brandon:
Efficient Encoding and Termination of Low-Density Parity-Check Convolutional Codes. GLOBECOM 2006 - 2005
- [c9]John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott:
Test and Characterization of a Variable-Capacity Multilevel DRAM. VTS 2005: 189-197 - 2003
- [c8]Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott:
An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. DFT 2003: 475- - [c7]Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott:
A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. MTDT 2003: 14-19 - 2002
- [c6]Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung:
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. MTDT 2002: 117-122 - [c5]Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott:
An Investigation into Crosstalk Noise in DRAM Structures. MTDT 2002: 123- - 2001
- [c4]Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn:
Design of an Embedded Fully-Depleted SOI SRAM. MTDT 2001: 13- - 1999
- [c3]Peter M. Nyasulu, Ralph Mason, W. Martin Snelgrove, Duncan G. Elliott:
Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system. CICC 1999: 631-634 - [c2]C. Wickman, Duncan G. Elliott, Bruce F. Cockburn:
Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. DFT 1999: 319- - [c1]Gershom Birk, Duncan G. Elliott, Bruce F. Cockburn:
A Comparative Simulation Study of Four Multilevel DRAMs. MTDT 1999: 102-109
Coauthor Index
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