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ORCIDAzad Naeemi
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Journal Articles
- 2023
[j5]Liuting Shang
, Azad Naeemi, Chenyun Pan:
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. IEEE Open J. Comput. Soc. 4: 50-61 (2023)- 2019
- [j4]Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu:
A Mixed Signal Architecture for Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 15(2): 19:1-19:26 (2019) - 2018
- [j3]Aditya Anupam, Ridhima Gupta, Azad Naeemi, Nassim Jafarinaimi:
Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics. IEEE Trans. Educ. 61(1): 29-37 (2018) - 2015
- [j2]Chenyun Pan, Azad Naeemi:
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 75-87 (2015) - 2013
- [j1]Shaloo Rakheja, Vachan Kumar, Azad Naeemi:
Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects. Proc. IEEE 101(7): 1740-1765 (2013)
Conference and Workshop Papers
- 2022
- [c35]Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu:
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. IMW 2022: 1-4 - 2020
- [c34]Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli:
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE 2020: 133-138 - 2019
- [c33]Aditya Anupam, Shubhangi Gupta, Azad Naeemi, Nassim Parvin:
Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games. CHI PLAY (Companion) 2019: 323-331 - 2018
- [c32]William Scott, Jonathan Jeffrey, Blake Heard, Dmitri E. Nikonov, Ian A. Young, Sasikanth Manipatruni, Azad Naeemi, Rouhollah Mousavi Iraei:
Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning. ACM Southeast Regional Conference 2018: 7:1-7:5 - [c31]Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi:
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC 2018: 28:1-28:6 - [c30]Victor Huang, Chenyun Pan, Azad Naeemi:
Generic system-level modeling and optimization for beyond CMOS device applications. ISQED 2018: 196-200 - 2017
- [c29]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - [c28]Chenyun Pan, Azad Naeemi:
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. DATE 2017: 133-138 - 2016
- [c27]Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi:
Device/system performance modeling of stacked lateral NWFET logic. ISQED 2016: 215-220 - [c26]Javaneh Mohseni, Chenyun Pan, Azad Naeemi:
Performance modeling and optimization for on-chip interconnects in 3D memory arrays. ISQED 2016: 252-257 - [c25]Divya Prasad, Chenyun Pan, Azad Naeemi:
Impact of interconnect variability on circuit performance in advanced technology nodes. ISQED 2016: 398-404 - 2015
- [c24]Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi:
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. ISQED 2015: 599-603 - 2014
- [c23]Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja:
BEOL Scaling Limits and Next Generation Technology Prospects. DAC 2014: 26:1-26:6 - [c22]Rose Peng, Bill Dorn, Azad Naeemi, Nassim Jafarinaimi:
Interactive visualizations for teaching quantum mechanics and semiconductor physics. FIE 2014: 1-4 - [c21]Sou-Chi Chang, Ahmet Ceyhan, Vachan Kumar, Azad Naeemi:
Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. ISLPED 2014: 63-68 - [c20]Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi:
An analytical approach to system-level variation analysis and optimization for multi-core processor. ISQED 2014: 99-106 - [c19]Nickvash Kani, Azad Naeemi:
Pipeline design in spintronic circuits. NANOARCH 2014: 110-115 - [c18]Nickvash Kani, Azad Naeemi:
Wiring resource minimization for physically-complex Network-on-Chip architectures. SoCC 2014: 261-266 - 2013
- [c17]Chenyun Pan, Ahmet Ceyhan, Azad Naeemi:
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. ISQED 2013: 196-202 - [c16]Ahmet Ceyhan, Azad Naeemi:
Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. ISQED 2013: 203-209 - [c15]Shaloo Rakheja, Vachan Kumar, Azad Naeemi:
Performance modeling for interconnects for conventional and emerging switches. SLIP 2013: 1-9 - 2012
- [c14]Ahmet Ceyhan, Azad Naeemi:
System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. ICICDT 2012: 1-4 - [c13]Chenyun Pan, Azad Naeemi:
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. ICICDT 2012: 1-5 - [c12]Chenyun Pan, Azad Naeemi:
Device- and system-level performance modeling for graphene P-N junction logic. ISQED 2012: 262-269 - [c11]Shaloo Rakheja, Azad Naeemi:
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. ISQED 2012: 283-290 - 2011
- [c10]Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee:
Power Aware Post-manufacture Tuning of Analog Nanocircuits. ETS 2011: 57-62 - [c9]Shaloo Rakheja, Azad Naeemi:
Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. ISQED 2011: 736-744 - 2010
- [c8]James D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali:
Nanoelectronics in retrospect, prospect and principle. ISSCC 2010: 31-35 - 2008
- [c7]Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl:
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC 2008: 663-670 - [c6]Azad Naeemi, James D. Meindl:
Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD 2008: 400-405 - 2007
- [c5]Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl:
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC 2007: 841-844 - [c4]Azad Naeemi, Reza Sarvari, James D. Meindl:
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC 2007: 568-573 - [c3]Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl:
IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD 2007: 560-567 - [c2]Azad Naeemi, James D. Meindl:
Carbon nanotube interconnects. ISPD 2007: 77-84 - 2006
- [c1]Azad Naeemi, Muhannad S. Bakir:
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. SoCC 2006: 323-324
Informal and Other Publications
- 2024
- [i10]Siri Narla, Piyush Kumar, Mohammad Adnaan, Azad Naeemi:
Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search. CoRR abs/2403.15328 (2024) - 2023
- [i9]Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Kang Wang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto:
Roadmap for Unconventional Computing with Nanotechnology. CoRR abs/2301.06727 (2023) - 2021
- [i8]Hai Li, Dmitri E. Nikonov, Chia-Ching Lin, Kerem Yunus Çamsari, Yu-Ching Liao, Chia-Sheng Hsu, Azad Naeemi, Ian A. Young:
Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. CoRR abs/2110.10890 (2021) - 2018
- [i7]Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu:
A mixed signal architecture for convolutional neural networks. CoRR abs/1811.02636 (2018) - 2017
- [i6]Chenyun Pan, Azad Naeemi:
Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. CoRR abs/1711.04295 (2017) - [i5]Rouhollah Mousavi Iraei, Nickvash Kani, Sourav Dutta, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young, John T. Heron, Azad Naeemi:
Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation. CoRR abs/1711.08568 (2017) - 2016
- [i4]Chenyun Pan, Azad Naeemi:
A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. CoRR abs/1604.04584 (2016) - [i3]Sou-Chi Chang, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi:
Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. CoRR abs/1609.06281 (2016) - [i2]Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu:
Non-volatile spin wave majority gate at the nanoscale. CoRR abs/1612.02170 (2016) - 2015
- [i1]Hamidreza Aghasi, Ruohollah Mousavi Iraei, Azad Naeemi, Ehsan Afshari:
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition. CoRR abs/1505.03065 (2015)
Coauthor Index
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last updated on 2024-11-06 21:35 CET by the dblp team
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