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2020 – today
- 2024
[j5]Tomoya Kashimata
, Masaya Yamasaki, Ryo Hidaka, Kosuke Tatsumura:
Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines. IEEE Access 12: 36606-36621 (2024)- [c8]Haruka Obata, Toshihisa Nabetani, Hayato Goto, Kosuke Tatsumura:
Ultra-High-Speed Optimization for 5G Wireless Resource Allocation by Simulated Bifurcation Machine. WCNC 2024: 1-6 - 2023
- [j4]Kosuke Tatsumura, Ryo Hidaka, Jun Nakayama, Tomoya Kashimata, Masaya Yamasaki:
Pairs-Trading System Using Quantum-Inspired Combinatorial Optimization Accelerator for Optimal Path Search in Market Graphs. IEEE Access 11: 104406-104416 (2023) - [j3]Kosuke Tatsumura, Ryo Hidaka, Jun Nakayama, Tomoya Kashimata, Masaya Yamasaki:
Real-Time Trading System Based on Selections of Potentially Profitable, Uncorrelated, and Balanced Stocks by NP-Hard Combinatorial Optimization. IEEE Access 11: 120023-120033 (2023) - [j2]Ryo Hidaka, Yohei Hamakawa, Jun Nakayama, Kosuke Tatsumura:
Correlation-Diversified Portfolio Construction by Finding Maximum Independent Set in Large-Scale Market Graph. IEEE Access 11: 142979-142991 (2023) - [i5]Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Camsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Kang Wang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto:
Roadmap for Unconventional Computing with Nanotechnology. CoRR abs/2301.06727 (2023) - [i4]Kosuke Tatsumura, Ryo Hidaka, Jun Nakayama, Tomoya Kashimata, Masaya Yamasaki:
Pairs-trading System using Quantum-inspired Combinatorial Optimization Accelerator for Optimal Path Search in Market Graphs. CoRR abs/2307.05923 (2023) - [i3]Kosuke Tatsumura, Ryo Hidaka, Jun Nakayama, Tomoya Kashimata, Masaya Yamasaki:
Real-time Trading System based on Selections of Potentially Profitable, Uncorrelated, and Balanced Stocks by NP-hard Combinatorial Optimization. CoRR abs/2307.06339 (2023) - [i2]Ryo Hidaka, Yohei Hamakawa, Jun Nakayama, Kosuke Tatsumura:
Correlation-diversified portfolio construction by finding maximum independent set in large-scale market graph. CoRR abs/2308.04769 (2023) - [i1]Tomoya Kashimata, Masaya Yamasaki, Ryo Hidaka, Kosuke Tatsumura:
Efficient and Scalable Architecture for Multiple-chip Implementation of Simulated Bifurcation Machines. CoRR abs/2311.17370 (2023) - 2021
- [c7]Kosuke Tatsumura:
Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation. HEART 2021: 1:1-1:6 - 2020
- [c6]Kosuke Tatsumura, Ryo Hidaka, Masaya Yamasaki, Yoshisato Sakai, Hayato Goto:
A Currency Arbitrage Machine Based on the Simulated Bifurcation Algorithm for Ultrafast Detection of Optimal Opportunity. ISCAS 2020: 1-5 - [c5]Masaya Yamasaki, Ryo Hidaka, Yoshisato Sakai, Jun Yamaguchi, Yasuhito Nakamura, Hayato Goto, Kosuke Tatsumura:
Live Demonstration: Capturing Short-Lived Currency Arbitrage Opportunities with a Simulated Bifurcation Algorithm-Based Trading System. ISCAS 2020: 1
2010 – 2019
- 2019
- [c4]Kosuke Tatsumura, Alexander Dixon, Hayato Goto:
FPGA-Based Simulated Bifurcation Machine. FPL 2019: 59-66 - 2018
- [j1]Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz:
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 6:1-6:22 (2018) - 2017
- [c3]Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz:
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. FPGA 2017: 115-124 - 2016
- [c2]Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz:
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. FPT 2016: 4-11 - 2014
- [c1]Kosuke Tatsumura, Masato Oda, Shinichi Yasuda:
A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs. FPT 2014: 215-222
Coauthor Index
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