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Chandan Karfa
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Journal Articles
- 2023
- [j22]Debabrata Senapati
, Arnab Sarkar
, Chandan Karfa
:
Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2447-2460 (2023) - [j21]Priyanka Panigrahi
, Chandan Karfa
:
Translation Validation of Information Leakage of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3585-3598 (2023) - [j20]Debabrata Senapati
, Kousik Rajesh
, Chandan Karfa
, Arnab Sarkar
:
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Design Autom. Electr. Syst. 28(6): 99:1-99:22 (2023) - 2022
- [j19]Surajit Das
, Chandan Karfa
, Santosh Biswas
:
Accelerating NoC Verification Using a Complete Model and Active Window. IEEE Access 10: 88985-88999 (2022) - [j18]Surajit Das
, Chandan Karfa
:
Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC. IEEE Embed. Syst. Lett. 14(2): 67-70 (2022) - [j17]Priyanka Panigrahi
, Vemuri Sahithya, Chandan Karfa
, Prabhat Mishra
:
Secure Register Allocation for Trusted Code Generation. IEEE Embed. Syst. Lett. 14(3): 127-130 (2022) - [j16]Debabrata Senapati
, Arnab Sarkar
, Chandan Karfa
:
PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms. IEEE Trans. Computers 71(2): 421-435 (2022) - [j15]Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza
, Yom Nigam, T. M. Abdul Khader, Chandan Karfa
:
FastSim: A Fast Simulation Framework for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1371-1385 (2022) - [j14]Mohammed Abderehman
, Rupak Gupta, Theegala Rakesh Reddy, Chandan Karfa:
BLAST: Belling the Black-Hat High-Level Synthesis Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3661-3672 (2022) - [j13]Priyanka Panigrahi
, Abhik Paul, Chandan Karfa
:
Quantifying Information Leakage for Security Verification of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4385-4396 (2022) - 2021
- [j12]Ramanuj Chouksey, Sachin Kumar Maddheshiya, Chandan Karfa
:
VP_TT: A value propagation based equivalence checker for testability transformations. IET Softw. 15(1): 147-159 (2021) - [j11]Debabrata Senapati
, Arnab Sarkar
, Chandan Karfa
:
HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Embed. Comput. Syst. 20(5s): 106:1-106:26 (2021) - 2020
- [j10]Surajit Das
, Chandan Karfa
, Santosh Biswas
:
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1016-1029 (2020) - [j9]Ramanuj Chouksey
, Chandan Karfa
:
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1638-1651 (2020) - 2019
- [j8]Chandan Karfa
, Dipankar Sarkar, Chittaranjan Mandal:
Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. 4(3): 276-289 (2019) - [j7]Ramanuj Chouksey, Chandan Karfa
, Kunal Banerjee, Pankaj Kumar Kalita, Purandar Bhaduri
:
Counter-example generation procedure for path-based equivalence checkers. IET Softw. 13(4): 280-285 (2019) - [j6]Ramanuj Chouksey
, Chandan Karfa
, Purandar Bhaduri
:
Translation Validation of Code Motion Transformations Involving Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1378-1382 (2019) - 2014
- [j5]Kunal Banerjee, Chandan Karfa
, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1180-1193 (2014) - 2013
- [j4]Chandan Karfa
, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1787-1800 (2013) - 2012
- [j3]Chandan Karfa
, Chittaranjan A. Mandal, Dipankar Sarkar:
Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. 17(3): 30:1-30:37 (2012) - 2010
- [j2]Chandan Karfa
, Dipankar Sarkar, Chitta Mandal:
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 479-492 (2010) - 2008
- [j1]Chandan Karfa
, Dipankar Sarkar, Chitta Mandal, P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 556-569 (2008)
Conference and Workshop Papers
- 2024
- [c32]Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati:
RTL Simulation Acceleration with Machine Learning Models. ISQED 2024: 1-7 - [c31]Debabrata Senapati, Dharmendra Maurya, Arnab Sarkar, Chandan Karfa:
ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems. VLSID 2024: 354-359 - [c30]Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa:
SRIL: Securing Registers from Information Leakage at Register Transfer Level. VLSID 2024: 492-498 - [c29]Praveen Karmakar, Marpina Bharani, Chandan Karfa:
Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. VLSID 2024: 517-522 - 2023
- [c28]Priyanka Panigrahi, Chandan Karfa:
An Investigation into the Security of Register Allocation with Spilling and Splitting. ISVLSI 2023: 1-6 - 2022
- [c27]Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa:
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications. DSD 2022: 67-74 - [c26]Gagan Gayari, Chandan Karfa, Prithwijit Guha:
GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking. ACM Great Lakes Symposium on VLSI 2022: 123-126 - [c25]Debabrata Senapati
, Arnab Sarkar, Chandan Karfa:
Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems. ICDCN 2022: 234-235 - [c24]Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay:
Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking. ISQED 2022: 1-6 - [c23]Mohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa:
DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis. ISQED 2022: 64-70 - 2021
- [c22]Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri
:
HOST: HLS Obfuscations against SMT ATtack. DATE 2021: 32-37 - [c21]Mohammed Abderehman, Rupak Gupta, Chandan Karfa:
Reverse Engineering Register to Variable Mapping in High-level Synthesis. ISVLSI 2021: 37-42 - 2020
- [c20]Melbin John, Aadil Hoda, Ramanuj Chouksey, Chandan Karfa:
SAT Based Partial Attack on Compound Logic Locking. AsianHOST 2020: 1-6 - [c19]Chandan Karfa
, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri
:
Is Register Transfer Level Locking Secure? DATE 2020: 550-555 - [c18]Pankaj Kumar Kalita, Ramanuj Chouksey, Chandan Karfa
:
Automatic Inverse Operation Detection and its Impact in High-level Synthesis. VDAT 2020: 1-4 - 2019
- [c17]Ramanuj Chouksey, Chandan Karfa
, Purandar Bhaduri
:
Formal Verification of Optimizing Transformations during High-level Synthesis. ISEC 2019: 27:1-27:5 - [c16]Priyanka Panigrahi
, Rajesh Kumar Jha
, Chandan Karfa
:
User Guided Register Manipulation in Digital Circuits. VDAT 2019: 468-481 - [c15]Ramanuj Chouksey, Chandan Karfa
, Purandar Bhaduri
:
Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. VLSID 2019: 377-382 - 2018
- [c14]Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa
, Pankaj Kumar Kalita:
Automatic detection of inverse operations while avoiding loop unrolling. ICSE (Companion Volume) 2018: 175-176 - [c13]Kunal Banerjee, Chandan Karfa
:
Compiler-agnostic Translation Validation. ISEC 2018: 22:1 - 2017
- [c12]Ramanuj Chouksey, Chandan Karfa
, Purandar Bhaduri
:
Translation Validation of Loop Invariant Code Optimizations Involving False Computations. VDAT 2017: 767-778 - [c11]Surajit Das, Chandan Karfa
, Santosh Biswas:
xMAS Based Accurate Modeling and Progress Verification of NoCs. VDAT 2017: 792-804 - 2013
- [c10]Chandan Karfa
, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of KPN Level Transformations. VLSI Design 2013: 338-343 - 2012
- [c9]Kunal Banerjee, Chandan Karfa
, Dipankar Sarkar, Chittaranjan Mandal:
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED 2012: 67-71 - 2011
- [c8]Chandan Karfa
, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal:
Equivalence Checking of Array-Intensive Programs. ISVLSI 2011: 156-161 - [c7]Chandan Karfa
, Chitta Mandal, Dipankar Sarkar:
Verification of Register Transfer Level Low Power Transformations. ISVLSI 2011: 313-314 - 2010
- [c6]Chandan Karfa
, Dipankar Sarkar, Chittaranjan A. Mandal:
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI 2010: 428-433 - 2007
- [c5]Chandan Karfa
, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade:
Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434 - [c4]Chandan Karfa
, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade:
Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140 - 2006
- [c3]Santosh Biswas, Chandan Karfa
, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra:
Fairness of transitions in diagnosability analysis of hybrid systems. ACC 2006: 1-6 - [c2]Chandan Karfa
, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78 - [c1]Chandan Karfa
, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146
Informal and Other Publications
- 2024
- [i4]Bhabesh Mali, Karthik Maddala, Sweeya Reddy, Vatsal Gupta, Chandan Karfa, Ramesh Karri:
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation. CoRR abs/2402.00093 (2024) - [i3]Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa:
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. CoRR abs/2407.11806 (2024) - 2020
- [i2]Benjamin Tan
, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020) - 2019
- [i1]Kunal Banerjee, Chandan Karfa:
A Quick Introduction to Functional Verification of Array-Intensive Programs. CoRR abs/1905.09137 (2019)
Coauthor Index
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