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2020 – today
- 2020
[c16]Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng:
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS 2020: 1-6
2010 – 2019
- 2016
- [j13]Shih-Hsu Huang, Chun-Hua Cheng:
Power-mode-aware buffer synthesis for low-power clock skew minimization. IEICE Electron. Express 13(14): 20160511 (2016) - 2014
- [c15]Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang:
Live demonstration: A low-power high-level synthesis system. APCCAS 2014: 165-166 - 2013
- [c14]Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE 2013: 1831-1836 - 2012
- [c13]Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang:
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS 2012: 627-630 - [c12]Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC 2012: 245-250 - [c11]Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng:
A formal approach to slack-driven high-level synthesis. ISCAS 2012: 584-587 - 2011
- [j12]Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng:
Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27(5): 1527-1543 (2011) - [c10]Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng:
Teaching three-dimensional system-in-package design automation in a semester course. MSE 2011: 52-55 - 2010
- [j11]Shih-Hsu Huang, Chun-Hua Cheng:
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26(6): 2249-2266 (2010)
2000 – 2009
- 2009
- [j10]Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng:
An ILP approach to surge current minimization in high-level synthesis. IEICE Electron. Express 6(14): 979-985 (2009) - [j9]Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan:
Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25(6): 1651-1670 (2009) - [j8]Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng:
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25(6): 1707-1722 (2009) - [j7]Shih-Hsu Huang, Chun-Hua Cheng:
Minimum-Period Register Binding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1265-1269 (2009) - [c9]Shih-Hsu Huang, Chun-Hua Cheng:
Timing driven power gating in high-level synthesis. ASP-DAC 2009: 173-178 - [c8]Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang:
Surge Current Minimization in High-level Synthesis. ISCAS 2009: 1513-1516 - 2008
- [j6]Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu:
Module binding for low power clock gating. IEICE Electron. Express 5(18): 762-768 (2008) - [j5]Shih-Hsu Huang, Chun-Hua Cheng:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 375-382 (2008) - [j4]Shih-Hsu Huang, Chun-Hua Cheng:
Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24(6): 1647-1668 (2008) - 2007
- [j3]Shih-Hsu Huang, Chun-Hua Cheng:
Operation scheduling for the synthesis of false loop free circuits. IEICE Electron. Express 4(14): 448-454 (2007) - [c7]Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion. DAC 2007: 970-975 - [c6]Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng:
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops 2007: 638-647 - 2006
- [j2]Shih-Hsu Huang, Chun-Hua Cheng:
An ILP Approach to the Slack Driven Scheduling Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1852-1858 (2006) - [c5]Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang:
Peak Power Minimization through Power Management Scheduling. APCCAS 2006: 868-871 - [c4]Shih-Hsu Huang, Chun-Hua Cheng:
Operation Scheduling for False Loop Free Circuits. APCCAS 2006: 1619-1622 - [c3]Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu:
Register binding for clock period minimization. DAC 2006: 439-444 - [c2]Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS 2006 - 2005
- [j1]Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng:
Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electron. Express 2(4): 108-114 (2005) - [c1]Shih-Hsu Huang, Chun-Hua Cheng:
A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) 2005: 5633-5636
Coauthor Index
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