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ORCIDSang H. Dhong
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2010 – 2019
- 2015
[c16]Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang:
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC 2015: 1-3- 2014
- [c15]Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC 2014: 1-4 - [c14]Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC 2014: 1-4 - [c13]Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang:
A 4-GHz universal high-frequency on-chip testing platform for IP validation. VTS 2014: 1-6 - 2013
- [c12]Jean-Pierre Colinge, Sang H. Dhong:
Prospective for nanowire transistors. CICC 2013: 1-8 - [c11]Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong:
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. CICC 2013: 1-4
2000 – 2009
- 2008
- [c10]Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong:
Challenges at 45nm and beyond. ICCAD 2008: 7 - 2007
- [j14]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - [c9]Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny:
Cell Broadband Engine Processor Design Methodology. CICC 2007: 711-716 - [c8]Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino:
Implementation of the 65nm Cell Broadband Engine. CICC 2007: 717-720 - 2006
- [j13]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - [j12]Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. IEEE J. Solid State Circuits 41(4): 759-771 (2006) - [j11]James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen:
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. IEEE J. Solid State Circuits 41(8): 1692-1706 (2006) - [c7]Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong:
A cycle accurate power estimation tool. ASP-DAC 2006: 867-870 - 2005
- [j10]Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman:
Power-Conscious Design of the Cell Processor's Synergistic Processor Element. IEEE Micro 25(5): 10-18 (2005) - [j9]Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara:
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. IEEE Micro 25(5): 30-38 (2005) - [c6]Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. IEEE Symposium on Computer Arithmetic 2005: 59-67 - [c5]Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor. ICCAD 2005: 111-117 - 2000
- [j8]David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka
, Daniel L. Stasiak, Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44(6): 799-822 (2000) - [j7]Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35(11): 1673-1679 (2000) - [c4]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717
1990 – 1999
- 1999
- [j6]Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong:
A 1-GHz logic circuit family with sense amplifiers. IEEE J. Solid State Circuits 34(5): 616-622 (1999) - 1998
- [j5]Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric:
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33(11): 1600-1608 (1998) - [j4]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi:
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18(3): 66-74 (1998) - [c3]Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki:
A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD 1998: 6-10 - [c2]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo:
Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23 - [c1]David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238 - 1995
- [j3]Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura:
A 64Kb - 32 DRAM for graphics applications. IBM J. Res. Dev. 39(1-2): 43-50 (1995) - [j2]Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata:
A low-noise TTL-compatible CMOS off-chip driver circuit. IBM J. Res. Dev. 39(1-2): 105-112 (1995) - [j1]Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira:
A variable precharge voltage sensing. IEEE J. Solid State Circuits 30(1): 25-28 (1995)
Coauthor Index
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