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2020 – today
- 2023
[c10]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans:
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2- 2022
- [c9]Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, Rongmei Chen, Anne Jourdain, N. Horiguchi:
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. ICICDT 2022: 51-54 - [c8]Stanislav Tyaginov, Alexander Makarov, Al-Moatasem Bellah El-Sayed, Adrian Vaisman Chasin, Erik Bury, Markus Jech, Michiel Vandemaele, Alexander Grill, An De Keersgieter, Mikhail I. Vexler, Geert Eneman, Ben Kaczer:
Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors. IRPS 2022: 6 - [c7]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285
2010 – 2019
- 2017
- [c6]Romain Ritzenthaler, Hans Mertens, An De Keersgieter, Jérôme Mitard, Dan Mocuta, N. Horiguchi:
Isolation of nanowires made on bulk wafers by ground plane doping. ESSDERC 2017: 300-303 - 2016
- [c5]Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134 - 2015
- [c4]Geert Eneman, An De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean:
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. ICICDT 2015: 1-4 - [c3]Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser, Philippe J. Roussel, Stanislav Tyaginov, M. Bina, Yannick Wimmer, Luis-Miguel Procel, Lionel Trojman, Felice Crupi, Gregory Pitner, Vamsi Putcha, Pieter Weckx, Erik Bury, Z. Ji, An De Keersgieter, Thomas Chiarella, Naoto Horiguchi, Guido Groeseneken, Aaron Thean:
Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3 - 2013
- [c2]Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, An De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha:
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC 2013: 159-162
2000 – 2009
- 2009
- [c1]Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais, An De Keersgieter, Stefan Kubicek, Augusto Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann:
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? ESSCIRC 2009: 84-87 - 2002
- [j1]Ben Kaczer, Robin Degraeve, Mahmoud Rasras, An De Keersgieter, K. Van de Mieroop, Guido Groeseneken:
Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study. Microelectron. Reliab. 42(4-5): 555-564 (2002)
Coauthor Index
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