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Jinshan Yue
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2020 – today
- 2024
- [j25]Woyu Zhang, Zhi Li, Xinyuan Zhang, Fei Wang, Shaocong Wang, Ning Lin, Yi Li, Jun Wang, Jinshan Yue, Chunmeng Dou, Xiaoxin Xu, Zhongrui Wang
, Dashan Shang
:
Fully Binarized Graph Convolutional Network Accelerator Based on In-Memory Computing with Resistive Random-Access Memory. Adv. Intell. Syst. 6(7) (2024) - [j24]Jinshan Yue
, Yongpan Liu
, Xiaoyu Feng
, Yifan He, Jingyu Wang
, Zhe Yuan, Mingtao Zhan
, Jiaxin Liu
, Jian-Wei Su
, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang
, Nan Sun, Chunmeng Dou
, Xueqing Li
, Ming Liu
, Huazhong Yang
:
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. IEEE J. Solid State Circuits 59(5): 1612-1627 (2024) - [j23]Shengzhe Yan
, Jinshan Yue
, Chaojie He
, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou
, Wenyu Sun
, Xueqing Li
, Chunmeng Dou
, Feng Zhang
, Huazhong Yang
, Yongpan Liu
, Ming Liu
:
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. IEEE J. Solid State Circuits 59(8): 2630-2643 (2024) - [j22]Hao Wu
, Yong Chen
, Yiyang Yuan
, Jinshan Yue
, Xiangqu Fu
, Qirui Ren
, Qing Luo
, Pui-In Mak
, Xinghua Wang
, Feng Zhang
:
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 689-702 (2024) - [j21]Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue
, Yongpan Liu
:
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 852-856 (2024) - [j20]Zhi Li, Rui Bao, Woyu Zhang, Fei Wang, Jun Wang, Renrui Fang, Haoxiong Ren, Ning Lin
, Jinshan Yue
, Chunmeng Dou
, Zhongrui Wang, Dashan Shang:
2T2R RRAM-Based In-Memory Hyperdimensional Computing Encoder for Spatio-Temporal Signal Processing. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2614-2618 (2024) - [j19]Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou:
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 283-290 (2024) - [c33]Guodong Yin, Yiming Chen, Mingyen Lee, Xirui Du, Yue Ke, Wenjun Tang, Zhonghao Chen, Mufeng Zhou, Jinshan Yue, Huazhong Yang, Hongyang Jia, Yongpan Liu, Xueqing Li:
A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. CICC 2024: 1-2 - [c32]Weizeng Li, Linfang Wang, Zhi Li, Wang Ye, Zhidao Zhou, Haiyang Zhou, Hanghang Gao, Jinshan Yue, Hongyang Hu, Fengman Liu, Qing Luo, Chunmeng Dou:
A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. ISCAS 2024: 1-4 - [c31]Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. ISSCC 2024: 578-580 - [c30]Linfang Wang, Weizeng Li, Zhidao Zhou, Hanghang Gao, Zhi Li, Wang Ye, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Chunmeng Dou, Qi Liu, Ming Liu:
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. ISSCC 2024: 582-584 - 2023
- [j18]Shengzhe Yan, Zhaori Cong, Nianduan Lu, Jinshan Yue, Qing Luo:
Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. Sci. China Inf. Sci. 66(10) (2023) - [j17]Wang Ye
, Linfang Wang
, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue
, Hongyang Hu
, Xiaoxin Xu
, Jianguo Yang
, Jing Liu
, Dashan Shang
, Feng Zhang
, Jinghui Tian, Chunmeng Dou
, Qi Liu
, Ming Liu:
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. IEEE J. Solid State Circuits 58(10): 2839-2850 (2023) - [j16]Yiming Chen
, Guodong Yin
, Mufeng Zhou
, Wenjun Tang
, Zekun Yang, Mingyen Lee
, Xirui Du
, Jinshan Yue
, Jiaxin Liu
, Huazhong Yang
, Yongpan Liu
, Xueqing Li
:
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2762-2773 (2023) - [j15]Xiangqu Fu
, Qirui Ren
, Hao Wu, Feibin Xiang, Qing Luo
, Jinshan Yue
, Yong Chen
, Feng Zhang
:
P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4938-4948 (2023) - [j14]Yifan He, Jinshan Yue, Xiaoyu Feng
, Yuxuan Huang
, Hongyang Jia
, Jingyu Wang
, Lu Zhang, Wenyu Sun, Huazhong Yang
, Yongpan Liu
:
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 416-420 (2023) - [j13]Yaolei Li
, Jinshan Yue, Jingyu Wang
, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang
, Huazhong Yang
, Yongpan Liu
:
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1179-1183 (2023) - [j12]Zhuoyu Dai, Feibin Xiang, Chaojie He, Zi Wang, Woyu Zhang, Yi Li
, Jinshan Yue
, Dashan Shang
:
A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3069-3073 (2023) - [j11]Hongyang Hu
, Xiwei Wang, Zi Wang, Haiyang Zhou, Danian Dong
, Jinshan Yue
, Wan Pang, Xiaoxin Xu
, Chunmeng Dou
:
A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2044-2052 (2023) - [c29]Xiaoyu Feng, Wenyu Sun, Shupei Fan, Chen Tang, Yixiong Yang, Jinshan Yue, Qingmin Liao, Huazhong Yang, Yongpan Liu:
A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator. AICAS 2023: 1-2 - [c28]Yixiong Yang, Ruoyang Liu, Chenhan Wei, Wenxun Wang, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing. CICC 2023: 1-2 - [c27]Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu:
A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. ISCAS 2023: 1-5 - [c26]Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC 2023: 130-131 - [c25]Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu:
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. ISSCC 2023: 252-253 - [c24]Wenyu Sun, Xiaoyu Feng, Chen Tang, Shupei Fan, Yixiong Yang, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network. ISSCC 2023: 328-329 - [c23]Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu:
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j10]Jinshan Yue
, Yongpan Liu
, Zhe Yuan, Xiaoyu Feng, Yifan He, Wenyu Sun
, Zhixiao Zhang, Xin Si
, Ruhui Liu
, Zi Wang, Meng-Fan Chang
, Chunmeng Dou
, Xueqing Li
, Ming Liu
, Huazhong Yang
:
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. IEEE J. Solid State Circuits 57(8): 2560-2573 (2022) - [j9]Yixiong Yang
, Yongpan Liu
, Zhe Yuan, Wenyu Sun
, Ruoyang Liu
, Jingyu Wang
, Jinshan Yue
, Xiaoyu Feng, Zhuqing Yuan
, Xueqing Li, Huazhong Yang
:
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications. IEEE J. Solid State Circuits 57(8): 2574-2585 (2022) - [j8]Jingyu Wang
, Songming Yu, Zhuqing Yuan, Jinshan Yue
, Zhe Yuan, Ruoyang Liu
, Yanzhi Wang
, Huazhong Yang
, Xueqing Li
, Yongpan Liu
:
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5043-5056 (2022) - [j7]Yuxuan Huang
, Yifan He, Jinshan Yue
, Huazhong Yang
, Yongpan Liu
:
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 518-529 (2022) - [j6]Yuxuan Huang
, Yifan He, Jingyu Wang
, Jinshan Yue
, Lu Zhang, Kaiwei Zou, Huazhong Yang
, Yongpan Liu
:
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3144-3148 (2022) - [c22]Linfang Wang, Junjie An, Wang Ye, Weizeng Li, Hanghang Gao, Yangu He, Jianfeng Gao, Jinshan Yue, Lingyan Fan, Chunmeng Dou:
RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference. APCCAS 2022: 497-500 - [c21]Yixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu:
Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation. ASP-DAC 2022: 442-447 - [c20]Yuxuan Huang
, Yifan He, Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. ASP-DAC 2022: 684-689 - [c19]Yifan He, Yuxuan Huang
, Jinshan Yue, Wenyu Sun, Lu Zhang, Yongpan Liu:
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations. ISCAS 2022: 3279-3283 - [i2]Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li:
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. CoRR abs/2212.04320 (2022) - 2021
- [j5]Jinshan Yue
, Yongpan Liu
, Ruoyang Liu
, Wenyu Sun
, Zhe Yuan, Yung-Ning Tu, Yi-Ju Chen, Ao Ren
, Yanzhi Wang, Meng-Fan Chang
, Xueqing Li, Huazhong Yang
:
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. IEEE J. Solid State Circuits 56(6): 1936-1948 (2021) - [c18]Yuxuan Huang
, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. ASP-DAC 2021: 126-131 - [c17]Yifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang:
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. ASP-DAC 2021: 813-818 - [c16]Chaoming Fang, Habib Derbyshire, Wenyu Sun, Jinshan Yue, Haobing Shi, Yongpan Liu:
A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection. A-SSCC 2021: 1-3 - [c15]Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices. ISOCC 2021: 197-198 - [c14]Jinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang
, Yipeng Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. ISSCC 2021: 238-240 - [c13]Songming Yu
, Lu Zhang, Jingyu Wang, Jinshan Yue, Zhuqing Yuan, Xueqing Li, Huazhong Yang, Yongpan Liu:
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme. NVMSA 2021: 1-6 - 2020
- [j4]Zhe Yuan, Yongpan Liu
, Jinshan Yue
, Yixiong Yang
, Jingyu Wang
, Xiaoyu Feng, Jian Zhao, Xueqing Li, Huazhong Yang
:
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. IEEE J. Solid State Circuits 55(2): 465-477 (2020) - [c12]Jingyu Wang, Songming Yu, Jinshan Yue, Zhe Yuan, Zhuqing Yuan, Huazhong Yang, Xueqing Li, Yongpan Liu:
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. DAC 2020: 1-6 - [c11]Xiaoyu Feng, Jinshan Yue, Zhe Yuan, Huazhong Yang, Yongpan Liu:
RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search. ISCAS 2020: 1-5 - [c10]Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. ISSCC 2020: 232-234 - [c9]Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. ISSCC 2020: 234-236 - [i1]Songming Yu, Yongpan Liu, Lu Zhang, Jingyu Wang, Jinshan Yue, Zhuqing Yuan, Xueqing Li, Huazhong Yang:
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning. CoRR abs/2010.06156 (2020)
2010 – 2019
- 2019
- [j3]Jinshan Yue
, Yongpan Liu
, Zhe Yuan, Zhibo Wang, Qingwei Guo
, Jinyang Li, Chengmo Yang, Huazhong Yang
:
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 277-281 (2019) - [c8]Xiaoyu Feng, Jinshan Yue, Qingwei Guo, Huazhong Yang, Yongpan Liu:
Accelerating CNN-RNN Based Machine Health Monitoring on FPGA. AICAS 2019: 184-188 - [c7]Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang:
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. ASP-DAC 2019: 146-151 - [c6]Zhe Yuan, Jingyu Wang, Yixiong Yang, Jinshan Yue, Zhibo Wang, Xiaoyu Feng, Yanzhi Wang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. A-SSCC 2019: 61-64 - [c5]Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. ISSCC 2019: 138-140 - 2018
- [j2]Jinyang Li
, Yongpan Liu
, Hehe Li, Zhe Yuan, Chenchen Fu, Jinshan Yue
, Xiaoyu Feng, Chun Jason Xue, Jingtong Hu, Huazhong Yang:
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1671-1684 (2018) - [c4]Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu:
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. VLSI Circuits 2018: 33-34 - 2017
- [j1]Yongpan Liu
, Jinshan Yue, Hehe Li, Qinghang Zhao, Mengying Zhao
, Chun Jason Xue, Guangyu Sun, Meng-Fan Chang, Huazhong Yang:
Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1660-1673 (2017) - [c3]Jinyang Li, Qingwei Guo, Fang Su, Zhe Yuan, Jinshan Yue, Jingtong Hu, Huazhong Yang, Yongpan Liu:
CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). ICCAD 2017: 888-893 - [c2]Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li, Huazhong Yang:
CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks. ISLPED 2017: 1-6 - 2016
- [c1]Hehe Li, Yongpan Liu, Chenchen Fu, Chun Jason Xue, Donglai Xiang
, Jinshan Yue, Jinyang Li, Daming Zhang, Jingtong Hu
, Huazhong Yang:
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead. DAC 2016: 156:1-156:6
Coauthor Index
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