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ORCIDChunyu Peng
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- affiliation: Anhui University, Hefei, China
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Journal Articles
- 2025
[j67]Hongbiao Wu
, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng:
High-throughput in-memory bitwise computing based on a coupled dual-SRAM array with independent operands. Int. J. Circuit Theory Appl. 53(4): 2381-2397 (2025)- [j66]Chunyu Peng, Wei Hu, Hao Zheng, Wenjuan Lu, Chenghu Dai, Xiulong Wu, Zhiting Lin, Junning Chen:
Real-time bit-line leakage balance circuit with four-input low-offset SA considering threshold voltage for SRAM stability design. Int. J. Circuit Theory Appl. 53(4): 2427-2446 (2025) - [j65]Wenjuan Lu, Chuang Wang, Wei Hu, Chenghu Dai, Chunyu Peng, Zhiting Lin, Xiulong Wu:
Hybrid MOSFET-TFET 11T SRAM cell with high write speed and free half-selected disturbance. Microelectron. J. 156: 106498 (2025) - [j64]Wei Hu, Qizhong Zhang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Xiulong Wu:
Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy. Microelectron. J. 157: 106569 (2025) - [j63]Qiang Zhao, Ziming Wang, Chunhui Fan, Bin Qiang, Jitao Xu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu:
A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors. Microelectron. J. 159: 106638 (2025) - [j62]Shiyu Zhao, Qiang Zhao, Licai Hao, Hao Wang, Lang Tian, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
A double-modules interlocking triple-node upset-tolerant latch design. Microelectron. J. 159: 106647 (2025) - [j61]Chenghu Dai, Jianhao Zhang, Ruixuan Wang, Junbo Chen, Wei Hu, Licai Hao, Wenjuan Lu, Zhiting Lin, Chunyu Peng, Xiulong Wu:
A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits. Microelectron. J. 161: 106703 (2025) - [j60]Li Liu, Wei Hu, Zhen Yang, Yiming Wei, Chunyu Peng, Xiulong Wu, Zhiting Lin, Wenjuan Lu, Yongliang Zhou, Junning Chen:
A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance. Microelectron. J. 161: 106718 (2025) - [j59]Wenjuan Lu, Lubin Xiang, Ling Wang, Chunyu Peng, Chenghu Dai, Zhiting Lin, Xiulong Wu:
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W. IEEE Trans. Very Large Scale Integr. Syst. 33(4): 1073-1081 (2025) - [j58]Licai Hao, Lang Tian, Hao Wang, Shiyu Zhao, Qiang Zhao, Chunyu Peng, Chenghu Dai, Zhi-Ting Lin, Xiulong Wu:
A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate. IEEE Trans. Very Large Scale Integr. Syst. 33(4): 1108-1117 (2025) - [j57]Qiang Zhao, Qingyi Liu, Xinyi Zhang, Licai Hao, Xin Li, Shengyue Zhang, Chunyu Peng, Zhiting Lin, Xiulong Wu:
A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1373-1383 (2025) - 2024
- [j56]Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng, Xiulong Wu:
A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations. Microelectron. J. 144: 106087 (2024) - [j55]Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu:
A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC. Microelectron. J. 145: 106124 (2024) - [j54]Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin:
Configurable in-memory computing architecture based on dual-port SRAM. Microelectron. J. 147: 106163 (2024) - [j53]Zhiting Lin, Changxin Yue, Ke Li, Qiushi Feng, Siyan Li, Yue Zhao, Yuanyang Wang, Jiaqi Chen, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Chenghu Dai, Licai Hao, Xiulong Wu:
Cross-coupled 4T2R multi-logic in-memory computing circuit design. Microelectron. J. 147: 106179 (2024) - [j52]Chunyu Peng, Shengyuan Yan, Huayi Ding, Yana Wang, Wenjuan Lu, Chenghu Dai, Xin Li, Wei Hu, Xiulong Wu:
High energy efficient and configurable CIM macro for image processing. Microelectron. J. 148: 106212 (2024) - [j51]Shiyu Zhao, Qiang Zhao, Licai Hao, Chunyu Peng, Yaling Wang, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
Design of polarity hardening SRAM for mitigating single event multiple node upsets. Microelectron. J. 149: 106214 (2024) - [j50]Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng:
An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. Microelectron. J. 151: 106308 (2024) - [j49]Zhiting Lin, Runru Yu, Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu:
A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC. Microelectron. J. 153: 106397 (2024) - [j48]Qiang Zhao, Jitao Xu, Chunhui Fan, Ziming Wang, Ruitong Hu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu:
An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor. Microelectron. J. 154: 106444 (2024) - [j47]Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu:
Corrigendum to "A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC" [145, March 2024, 106124. Microelectron. J. 154: 106473 (2024) - [j46]Chunyu Peng, Lang Tian, Licai Hao, Qiang Zhao, Chenghu Dai, Zhiting Lin, Xiulong Wu:
High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 60(5): 6550-6561 (2024) - [j45]Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu:
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 187-200 (2024) - [j44]Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, JingXue Zhong, Xiulong Wu, Chunyu Peng:
Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4019-4031 (2024) - [j43]Li Liu, Dele Tai, Bin Qiang, Lijun Guan, Chunyu Peng, Chenghu Dai, Licai Hao, Wenjuan Lu, Zhiting Lin, Qiang Zhao, Xiulong Wu:
Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1759-1763 (2024) - [j42]Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 597-608 (2024) - [j41]Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024) - 2023
- [j40]Licai Hao, Bin Qiang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Li Liu, Qiang Zhao, Xiulong Wu, Fei Sun:
Radiation-hardened 14T SRAM cell by polar design for space applications. IEICE Electron. Express 20(13): 20230083 (2023) - [j39]Qiang Zhao, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu:
Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments. Int. J. Circuit Theory Appl. 51(1): 398-409 (2023) - [j38]Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Junning Chen:
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. IEEE J. Solid State Circuits 58(5): 1472-1486 (2023) - [j37]Licai Hao, Li Liu, Qi Shi, Bin Qiang, Zhengya Li, Nianlong Liu, Chenghu Dai, Qiang Zhao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
Design of radiation-hardened memory cell by polar design for space applications. Microelectron. J. 132: 105691 (2023) - [j36]Chenghu Dai, Yuanyuan Du, Qi Shi, Ruixuan Wang, Hao Zheng, Wenjuan Lu, Chunyu Peng, Licai Hao, Zhiting Lin, Xiulong Wu:
Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design. Microelectron. J. 132: 105699 (2023) - [j35]Pengfei Li, Xiuying Wang, Yin Zhang, Haoyu Wang, Jianjie Lu, Qiang Zhao, Licai Hao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology. Microelectron. J. 141: 105954 (2023) - [j34]Zuheng Wu, Changwei Zhang, Jianxun Zou, Chunyu Peng, Xiulong Wu:
Threshold Switching Memristor-Based Voltage Regulative Circuit. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1034-1038 (2023) - [j33]Zhiting Lin, Min Chen, Peng Sun, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng:
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 522-531 (2023) - [j32]Zhiting Lin, Shaoying Zhang, Qian Jin, Jianping Xia, Yunwei Liu, Kefeng Yu, Jian Zheng, Xiaoming Xu, Xing Fan, Ke Li, Zhongzhen Tong, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao:
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 776-788 (2023) - 2022
- [j31]Qiang Zhao, Hanwen Dong, Licai Hao, Xiuying Wang, Chunyu Peng, Xiulong Wu:
Novel radiation-hardened latch design for space-radiation environments. IEICE Electron. Express 19(13): 20220170 (2022) - [j30]Yue Zhao, Jinkai Wang, Zhongzhen Tong, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin:
An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset. Microelectron. J. 128: 105578 (2022) - [j29]Jin Zhang, Zhiting Lin, Xiulong Wu, Zhongzhen Tong, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Hongbiao Wu, Junning Chen:
In-Memory Multibit Multiplication Based on Bitline Shifting. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 354-358 (2022) - [j28]Pei Huang, Kuan-Chang Chang, Junlin Ge, Chunyu Peng, Xiulong Wu, Junning Chen, Zhiting Lin:
Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2011-2015 (2022) - [j27]Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen:
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 566-578 (2022) - 2021
- [j26]Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao, Xuan Li, Junning Chen:
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. IEEE J. Solid State Circuits 56(8): 2550-2562 (2021) - [j25]Zhiting Lin, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, Junning Chen:
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. IEEE J. Solid State Circuits 56(9): 2832-2844 (2021) - [j24]Chunyu Peng, Zhou Yang, Zhiting Lin, Xiulong Wu, Xuan Li:
Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 466-470 (2021) - [j23]Zhiting Lin, Luanyun Li, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao:
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2628-2632 (2021) - 2020
- [j22]Wenjuan Lu, Guoying Qin, Zhiting Lin, Xiulong Wu, Chunyu Peng:
A new reading mode based on balanced pre-charging and group decoding. IEICE Electron. Express 17(24): 20200360 (2020) - [j21]Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang, Chunyu Peng, Xiulong Wu, Junning Chen:
Challenges and Solutions of the TFET Circuit Design. IEEE Trans. Circuits Syst. 67-I(12): 4918-4931 (2020) - [j20]Zhiting Lin, Yong Wang, Chunyu Peng, Xiulong Wu, Xuan Li, Junning Chen:
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 607-619 (2020) - [j19]Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu:
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 848-852 (2020) - [j18]Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen:
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1316-1320 (2020) - 2019
- [j17]Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
An inverter chain with parallel output nodes for eliminating single-event transient pulse. IEICE Electron. Express 16(4): 20181118 (2019) - [j16]Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A single event upset tolerant latch with parallel nodes. IEICE Electron. Express 16(11): 20190208 (2019) - [j15]Yuyong Jia, Zhengping Li, Chunyu Peng:
A high performance radiation-hardened SRAM cell based on Quatro. IEICE Electron. Express 16(16): 20190335 (2019) - [j14]Qiang Zhao, Chunyu Peng, Changyong Liu, Xiulong Wu:
Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS. IEICE Electron. Express 16(17): 20190407 (2019) - [j13]Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng:
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 407-415 (2019) - 2018
- [j12]Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng:
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. IEICE Electron. Express 15(10): 20180332 (2018) - [j11]Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. IEICE Electron. Express 15(15): 20180604 (2018) - [j10]Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin:
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 584-588 (2018) - 2017
- [j9]Chunyu Peng, Ziyang Chen, Jingbo Zhang, Songsong Xiao, Changyong Liu, Xiulong Wu, Zhiting Lin:
A radiation harden enhanced Quatro (RHEQ) SRAM cell. IEICE Electron. Express 14(18): 20170784 (2017) - [j8]Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen:
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process. IEEE J. Solid State Circuits 52(3): 669-677 (2017) - 2016
- [j7]Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen:
Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier. IEICE Electron. Express 13(7): 20150951 (2016) - [j6]Chunyu Peng, Lijun Guan, Wenjuan Lu, Xiulong Wu, Xincun Ji:
Read/write margin enhanced 10T SRAM for low voltage application. IEICE Electron. Express 13(12): 20160382 (2016) - [j5]Chunyu Peng, Xiangwen An, Zhiting Lin, Xiulong Wu, Wei Hong:
Additive-calibration scheme for leakage compensation of low voltage SRAM. IEICE Electron. Express 13(18): 20160720 (2016) - 2015
- [j4]Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen:
A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier. IEICE Electron. Express 12(5): 20150102 (2015) - [j3]Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen:
Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. IEICE Electron. Express 12(7): 20158001 (2015) - [j2]Shoubiao Tan, Li Liu, Chunyu Peng, Ling Shao:
Image-to-class distance ratio: A feature filtering metric for image classification. Neurocomputing 165: 211-221 (2015) - [j1]Shoubiao Tan, Wenjuan Lu, Chunyu Peng, Zhengping Li, Youwu Tao, Junning Chen:
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier. Frontiers Inf. Technol. Electron. Eng. 16(8): 700-706 (2015)
Conference and Workshop Papers
- 2024
- [c5]Zhiting Lin, Yunlong Liu, Yaling Wang, Yue Zhao, Chunyu Peng, Xiulong Wu:
SRAM-Based Digital CIM Macro for Linear Interpolation and MAC. ISCAS 2024: 1-5 - [c4]Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu:
A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. ISCAS 2024: 1-5 - 2023
- [c3]Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang:
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. ESSDERC 2023: 13-16 - [c2]Yincong Wang, Shoubiao Tan, Chunyu Peng:
MS3DAAM: Multi-scale 3-D Analytic Attention Module for Convolutional Neural Networks. ICONIP (1) 2023: 104-117 - 2015
- [c1]Zhiting Lin, Chunyu Peng, Xiulong Wu, Xiufang Jiang:
Human dynamics in mobile social networks: A study of inter-node relationships. FSKD 2015: 806-810
Coauthor Index
Zhi-Ting Lin
aka: Zhiting Lin
aka: Zhiting Lin
[j67] [j66] [j65] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j54] [j53] [j51] [j49] [j48] [j46] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j33] [j32] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j13] [j12] [j11] [j10] [j9] [j8] [j5] [c5] [c1]
[j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j6] [j5] [c5] [c4] [c3] [c1]
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