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2020 – today
- 2024
[j12]Junnosuke Suzuki
, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12: 2057-2073 (2024)- [j11]Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12: 6926-6940 (2024) - [j10]Philippos Papaphilippou, Thiem Van Chu:
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers. IEEE Trans. Computers 73(5): 1414-1426 (2024) - [j9]Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura:
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024) - [c32]Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS 2024: 377-381 - [c31]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC 2024: 785-791 - [c30]Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura:
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO 2024 - [c29]Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE 2024: 1-2 - [c28]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE 2024: 1-2 - [c27]Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE 2024: 1-2 - [c26]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE 2024: 1-2 - [c25]Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. IJCNN 2024: 1-8 - [i2]Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura:
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR abs/2402.14029 (2024) - 2023
- [j8]Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu:
An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration. IEEE Access 11: 5701-5713 (2023) - [j7]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106(12): 1969-1978 (2023) - [c24]Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS 2023: 1-3 - [c23]Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM 2023: 215 - [c22]Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura:
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC 2023: 42-43 - [c21]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG 2023: 11 - [c20]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485 - [c19]Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2 - [i1]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR abs/2312.03236 (2023) - 2022
- [j6]Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. 105-D(12): 2019-2031 (2022) - [c18]Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
Multicoated Supermasks Enhance Hidden Networks. ICML 2022: 17045-17055 - [c17]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops 2022: 414-420 - [c16]Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura:
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC 2022: 1-3 - 2021
- [j5]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11(2): 215-230 (2021) - [j4]Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11(2): 338-353 (2021) - [c15]Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT 2021: 1-10 - [c14]Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS 2021: 1-21 - 2020
- [c13]Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka:
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. FPGA 2020: 211-221 - [c12]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR 2020: 146-152 - [c11]Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR 2020: 215-220
2010 – 2019
- 2019
- [j3]Thiem Van Chu, Kenji Kise:
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes. IEICE Trans. Inf. Syst. 102-D(10): 1925-1941 (2019) - 2018
- [c10]Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise:
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. FCCM 2018: 197-204 - [c9]Thiem Van Chu, Kenji Kise:
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. FPL 2018: 419-426 - 2017
- [j2]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. 10(4): 27:1-27:27 (2017) - [c8]Susumu Mashimo, Thiem Van Chu, Kenji Kise:
High-Performance Hardware Merge Sorter. FCCM 2017: 1-8 - [c7]Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise:
Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip. MCSoC 2017: 83-90 - 2016
- [j1]Susumu Mashimo, Thiem Van Chu, Kenji Kise:
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News 44(4): 8-13 (2016) - [c6]Takuma Usui, Thiem Van Chu, Kenji Kise:
A Cost-Effective and Scalable Merge Sorter Tree on FPGAs. CANDAR 2016: 47-56 - [c5]Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda:
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS 2016: 1-8 - 2015
- [c4]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM 2015: 60-63 - [c3]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Ultra-fast NoC emulation on a single FPGA. FPL 2015: 1-8 - 2014
- [c2]Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise:
Ultrasmall: The smallest MIPS soft processor. FPL 2014: 1-4 - [c1]Thiem Van Chu, Shimpei Sato, Kenji Kise:
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC 2014: 215-222
Coauthor Index
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last updated on 2024-10-07 22:13 CEST by the dblp team
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