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Publication search results
found 83 matches
- 2024
- Tingran Chen, Wenjia Wang, Jiaqi Chen, Haotian Fu, Wente Yi, Bojun Cheng, He Zhang, Biao Pan:
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3214-3227 (2024) - 2023
- Miroslav N. Velev:
Automatic Formal Verification of RISC-V Pipelined Microprocessors with Fault Tolerance by Spatial Redundancy at a High Level of Abstraction. iFM 2023: 193-213 - 2022
- Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez, Giovanni Squillero:
Machine learning for hardware security: Classifier-based identification of Trojans in pipelined microprocessors. Appl. Soft Comput. 116: 108068 (2022) - Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger:
AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. DDECS 2022: 32-37 - 2021
- Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez, Giovanni Squillero:
A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores. DDECS 2021: 51-56 - 2018
- Anteneh Gebregiorgis, Mehdi Baradaran Tahoori:
Fine-Grained Energy-Constrained Microprocessor Pipeline Design. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 457-469 (2018) - Miroslav N. Velev:
Survey of Techniques for Efficient Solving of Boolean Formulas from Formal Verification of Pipelined, Superscalar, and VLIW Microprocessors at a High Level of Abstraction. ISAIM 2018 - 2016
- Yang Lin, Mark Zwolinski, Basel Halak:
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1688-1701 (2016) - Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS 2016: 297-300 - Anteneh Gebregiorgis, Mohammad Saber Golanbari, Saman Kiamehr, Fabian Oboril, Mehdi Baradaran Tahoori:
Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization. ISLPED 2016: 272-277 - 2015
- Yang Lin:
Cost-effective radiation hardened techniques for microprocessor pipelines. University of Southampton, UK, 2015 - Mohammad Abdur Rouf, Soontae Kim:
Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 131-141 (2015) - 2014
- Fabian Oboril, Mehdi Baradaran Tahoori:
Aging-Aware Design of Microprocessor Instruction Pipelines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 704-716 (2014) - Hu Chen, Sanghamitra Roy, Koushik Chakraborty:
DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors. DATE 2014: 1-6 - Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri:
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - Miroslav N. Velev, Ping Gao:
Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinality. ICCAD 2014: 676-683 - K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle:
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS 2014: 778-781 - Chen-Bo Hsu, James B. Kuo:
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits. ISIC 2014: 328-331 - K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle:
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC 2014: 1-6 - 2013
- Ching-Hwa Cheng:
Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor. VLSI Design 2013: 425105:1-425105:10 (2013) - Koushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, Dean Michael Ancajas:
Efficiently tolerating timing violations in pipelined microprocessors. DAC 2013: 102:1-102:8 - Paolo Bernardi, D. Boyang, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan:
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors. IDT 2013: 1-6 - 2012
- Miroslav N. Velev, Ping Gao:
Automated debugging of counterexamples in formal verification of pipelined microprocessors. ASP-DAC 2012: 689-694 - Ahmed M. Mahran:
A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor. CoRR abs/1203.0787 (2012) - 2011
- Miroslav N. Velev, Ping Gao:
Automatic formal verification of multithreaded pipelined microprocessors. ICCAD 2011: 679-686 - Miroslav N. Velev, Ping Gao:
Modular Schemes for Constructing Equivalent Boolean Encodings of Cardinality Constraints and Application to Error Diagnosis in Formal Verification of Pipelined Microprocessors. SARA 2011 - 2010
- Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Adaptive Pipeline voltage Scaling in High Performance Microprocessor. J. Circuits Syst. Comput. 19(8): 1817-1834 (2010) - Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:
Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444 - Miroslav N. Velev, Ping Gao:
Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors. ICFEM 2010: 355-370 - Panagiotis Manolios, Sudarshan K. Srinivasan:
Verifying Pipelines with BAT. Design and Verification of Microprocessor Systems for High-Assurance Applications 2010: 145-174
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