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ORCIDHe Zhang 0011
Person information
- affiliation (PhD 2021): Beihang University, Fert Beijing Insitute, MIIT Key Laboratory of Spintronics, Beijing, China
Other persons with the same name
- He Zhang — disambiguation page
- He Zhang 0001
![[0000-0002-9159-5331]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9159-5331")
(aka: He Jason Zhang) — Nanjing University, Software Institute, State Key Laboratory of Novel Software Technology, China (and 3 more) - He Zhang 0002 — Nanjing University of Science and Technology, School of Automation, China (and 1 more)
- He Zhang 0003 — Chinese Academy of Sciences, Institute of Semiconductors, State Key Laboratory on Integrated Optoelectronics, Beijing, China
- He Zhang 0004 — Adobe Inc., San Jose, CA, USA (and 1 more)
- He Zhang 0005 — Chinese Academy of Sciences, Institute of Atmospheric Physics, International Center for Climate and Environment Sciences, China
- He Zhang 0006 — Harbin Institute of Technology, Department of Electrical Engineering, China
- He Zhang 0007 — Xi'an Jiaotong University, School of Electronic and Information Engineering, China
- He Zhang 0008 — Chang'an University, Xi'an, China
- He Zhang 0009 — Aalto University, Helsinki, Finland
- He Zhang 0010 — Monash University, Faculty of Information Technology, Australia
- He Zhang 0012 — Monash University, Faculty of Information Technology, IT, Clayton, VIC, Australia
- He Zhang 0013 — University of Nottingham Ningbo China, Key Laboratory of More Electric Aircraft Technology of Zhejiang Province, China (and 1 more)
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2020 – today
- 2024
[j7]Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang:
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1130-1143 (2024)- 2023
- [j6]Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang:
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 7-20 (2023) - [c13]Qianlei Ou, Shixing Li, Chao Wang, He Zhang, Zhaohao Wang:
A Robust Time-based Error-Proofing Readout Scheme for MRAM. NANOARCH 2023: 13:1-13:3 - [c12]Linjun Jiang, Sifan Sun, Jinming Ge, He Zhang, Wang Kang:
An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network. NVMSA 2023: 44-49 - 2022
- [j5]Lichuan Luo, Dijun Liu, He Zhang, Youguang Zhang, Jinyu Bai, Wang Kang:
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture. CCF Trans. High Perform. Comput. 4(4): 421-434 (2022) - [j4]He Zhang, Junzhan Liu, Jinyu Bai, Sai Li, Lichuan Luo, Shaoqian Wei, Jianxin Wu, Wang Kang:
HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4465-4474 (2022) - [j3]Linjun Jiang, Erya Deng, He Zhang, Zhaohao Wang, Wang Kang, Weisheng Zhao:
A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2086-2090 (2022) - [j2]Biao Pan, Guangyao Wang, He Zhang, Wang Kang, Weisheng Zhao:
A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3044-3050 (2022) - [c11]He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao:
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. DAC 2022: 109-114 - 2021
- [c10]Lichuan Luo, He Zhang, Jinyu Bai, Youguang Zhang, Wang Kang, Weisheng Zhao:
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture. DATE 2021: 1865-1870 - [c9]He Zhang, Junzhan Liu, Kang Wang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao:
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. ICTA 2021: 123-124 - 2020
- [c8]Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik, Weisheng Zhao:
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques. DATE 2020: 1217-1222 - [c7]He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Deep Neural Network accelerator with Spintronic Memory. ACM Great Lakes Symposium on VLSI 2020: 51
2010 – 2019
- 2019
- [c6]Wang Kang, He Zhang, Weisheng Zhao:
Spintronic Memories: From Memory to Computing-in-Memory. NANOARCH 2019: 1-2 - 2018
- [j1]He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao:
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. IEEE Access 6: 64250-64260 (2018) - [c5]He Zhang, Wang Kang, Zhaohao Wang, Erya Deng, Youguang Zhang, Weisheng Zhao:
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory. APCCAS 2018: 382-385 - [c4]Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao:
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. NANOARCH 2018: 72-78 - 2017
- [c3]Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao:
Advanced Low Power Spintronic Memories beyond STT-MRAM. ACM Great Lakes Symposium on VLSI 2017: 299-304 - [c2]Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao:
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device. ICCD 2017: 613-616 - 2016
- [c1]He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao:
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM. NANOARCH 2016: 1-6
Coauthor Index
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last updated on 2024-05-23 23:49 CEST by the dblp team
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