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ORCIDRajendran Panda
- > Home > Persons > Rajendran Panda
Publications
- 2004
[j7]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1670-1677 (2004)- [c36]Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
A stochastic approach To power grid analysis. DAC 2004: 171-176 - 2003
- [j6]Rajendran Panda, Savithri Sundareswaran, David T. Blaauw:
Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Des. Test Comput. 20(3): 16-22 (2003) - [j5]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
:
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 49-66 (2003) - [j4]Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 337-345 (2003) - [c32]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276 - [c31]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957 - [c30]Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192 - [c29]D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel:
SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128 - [c28]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 - [c26]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176 - [c25]Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta:
Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-382 - 2002
- [j3]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw:
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 159-168 (2002) - [j2]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw:
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 79-90 (2002) - [c24]Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-463 - [c23]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 - [c22]Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy:
Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594 - [c21]Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj:
Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418 - [c20]Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh:
Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430 - [c19]Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh:
False-Noise Analysis Using Resolution Method. ISQED 2002: 437-442 - [c18]Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda:
Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83 - 2001
- [c16]Rajendran Panda, Savithri Sundareswaran, David T. Blaauw:
On the interaction of power distribution network with substrate. ISLPED 2001: 388-393 - 2000
- [c15]Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw:
On-chip inductance modeling and analysis. DAC 2000: 63-68 - [c14]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. DAC 2000: 150-155 - [c13]Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards:
Current signature compression for IR-drop analysis. DAC 2000: 162-167 - [c12]David T. Blaauw, Rajendran Panda, Abhijit Das:
Removing user specified false paths from timing graphs. DAC 2000: 270-273 - [c11]David T. Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang:
On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80 - [c10]David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda:
Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343 - [c9]Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju:
Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184 - [c8]Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw:
Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155 - 1999
- [c7]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw:
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441 - 1998
- [c6]Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw:
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391 - [c5]Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden:
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743 - [c3]David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
Emerging power management tools for processor design. ISLPED 1998: 143-148 - 1997
- [c1]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw:
Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662
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