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ORCIDNey Laert Vilar Calazans
Publications
- 2024
[c122]Carlos Gabriel de Araujo Gewehr
, Nicolas Moura, Lucas Luza, Eduardo Bernardon, Ney Calazans, Rafael Garibotti, Fernando Gehm Moraes:
Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems. LASCAS 2024: 1-5- 2023
- [c121]Eduardo Pereira, Lucas Luza, Nicolas Moura, Luciano Ost, Ney Calazans, Fernando Gehm Moraes, Rafael Garibotti:
Assessment of Communication Protocols' Latency in Co-processing Robotic Systems. NEWCAS 2023: 1-5 - [c120]Nicolas Moura, Joaquim Lucena, Eduardo Pereira, Ney Calazans, Luciano Ost, Fernando Moraes, Rafael Garibotti:
Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M Processors. SBCCI 2023: 1-6 - [c119]Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI 2023: 1-6 - 2019
- [c110]Luiz Carlos Moreira, José Fontebasso Neto, Walter Silva Oliveira, Thiago Ferauche, Guilherme Heck, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. SBCCI 2019: 34 - 2017
- [c109]Leonardo Rezende Juracy, Felipe B. Lazzarotto, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
XGT4: An industrial grade, open source tester for multi-gigabit networks. ICECS 2017: 252-255 - 2015
- [j13]Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 563-567 (2015) - [c92]Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS 2015: 1-4 - [c91]Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS 2015: 1-4 - [c90]Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira:
SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI 2015: 2:1-2:7 - 2014
- [j12]Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. 10(3): 313-320 (2014) - [j11]Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
MoNoC: A monitored network on chip with path adaptation mechanism. J. Syst. Archit. 60(10): 783-795 (2014) - [j9]Everton Alceu Carara, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Differentiated Communication Services for NoC-Based MPSoCs. IEEE Trans. Computers 63(3): 595-608 (2014) - [j8]Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1644-1647 (2014) - [c84]Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Moraes, Ney Calazans:
A monitored NoC with runtime path adaptation. ISCAS 2014: 1965-1968 - 2013
- [c78]Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Charge sharing aware NCL gates design. DFTS 2013: 212-217 - [c73]Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. ISSoC 2013: 1-6 - 2012
- [c64]Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans:
A generic FPGA emulation framework. ICECS 2012: 233-236 - [c60]Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans:
Impact of C-elements in asynchronous circuits. ISQED 2012: 437-343 - [c59]Carlos A. Petry, Eduardo Wächter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
A spectrum of MPSoC models for design space exploration and its use. RSP 2012: 30-35 - [c57]Thiago R. da Rosa, Vivian Larrea, Ney Calazans, Fernando Gehm Moraes:
Power consumption reduction in MPSoCs through DFS. SBCCI 2012: 1-6 - 2011
- [j7]Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres:
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Des. Test Comput. 28(5): 62-71 (2011) - [j6]César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin:
CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distributed Comput. 71(5): 714-728 (2011) - [c56]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans:
Adapting a C-element design flow for low power. ICECS 2011: 45-48 - [c54]Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping 2011: 193-198 - [c53]Thiago R. da Rosa, Guilherme Montez Guindani, Douglas de O. Cardoso, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
A self-adaptable distributed DFS scheme for NoC-based MPSoCs. SBCCI 2011: 203-208 - 2010
- [j5]Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Dynamic Task Mapping for MPSoCs. IEEE Des. Test Comput. 27(5): 26-35 (2010) - [c51]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 - [c50]Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes:
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. SBCCI 2010: 91-96 - [c48]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498 - 2009
- [c46]Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
HeMPS - a Framework for NoC-based MPSoC Generation. ISCAS 2009: 1345-1348 - [c45]Ewerson Carvalho, César A. M. Marcon, Ney Calazans, Fernando Moraes:
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. SoC 2009: 87-90 - [c44]Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ReConFig 2009: 24-29 - [c43]Guilherme Montez Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes:
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. ReConFig 2009: 30-35 - 2008
- [j4]César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2(6): 471-482 (2008) - [c41]Guilherme Montez Guindani, Cezar Reinbrecht, Thiago Raupp da Rosa, Ney Calazans, Fernando Gehm Moraes:
NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478 - [c38]Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans:
MOTIM: an industrial application using nocs. SBCCI 2008: 182-187 - 2007
- [c36]Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans:
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546 - [c35]César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392 - [c34]Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes:
MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI 2007: 451-452 - [c33]Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI 2007: 459-460 - [c32]Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes:
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30 - [c31]Luis Carlos Caruso, Guilherme Montez Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes:
SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. IEEE International Workshop on Rapid System Prototyping 2007: 27-33 - [c30]Ewerson Carvalho, Ney Calazans, Fernando Moraes:
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. IEEE International Workshop on Rapid System Prototyping 2007: 34-40 - [c29]Leonel Tedesco, Fernando Moraes, Ney Calazans:
Buffer sizing for QoS flows in wormhole packet switching NoCs. SBCCI 2007: 99-104 - [c28]Everton Carara, Fernando Moraes, Ney Calazans:
Router architecture for high-performance NoCs. SBCCI 2007: 111-116 - [c27]Aline Mello, Ney Calazans, Fernando Moraes:
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. VLSI-SoC (Selected Papers) 2007: 1-22 - [i2]César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel:
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. CoRR abs/0710.4738 (2007) - [i1]Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes:
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. CoRR abs/0710.4843 (2007) - 2006
- [c25]Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes:
Reconfigurable Systems Enabled by a Network-on-Chip. FPL 2006: 1-4 - [c24]Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
Evaluation of current QoS Mechanisms in Networks on Chip. SoC 2006: 1-4 - [c23]Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes:
Infrastructure for dynamic reconfigurable systems: choices and trade-offs. SBCCI 2006: 44-49 - [c22]Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes:
Application driven traffic modeling for NoCs. SBCCI 2006: 62-67 - 2005
- [c21]Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans:
MAIA: a framework for networks on chip generation and verification. ASP-DAC 2005: 49-52 - [c20]César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel:
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE 2005: 502-507 - [c17]Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
Virtual channels in networks on chip: implementation and evaluation on hermes NoC. SBCCI 2005: 178-183 - [c16]Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes:
Traffic generation and performance evaluation for mesh-based NoCs. SBCCI 2005: 184-189 - [c15]José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin:
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201 - [c14]César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis:
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194 - 2004
- [j3]Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost:
HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integr. 38(1): 69-93 (2004) - [c13]Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes:
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239 - [c12]Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato:
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL 2004: 1042-1046 - [c11]Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes:
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. SBCCI 2004: 10-15 - 2003
- [c10]Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans:
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE 2003: 11122-11123 - [c9]Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans:
Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS 2003: 177 - [c8]Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara:
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355- - [c7]Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans:
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323 - 2002
- [c6]César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Prototyping of embedded digital systems from SDL language: a case study. HLDVT 2002: 133-138 - [c5]Alexandre M. Amory, Fernando Moraes, Leandro A. Oliveira, Ney Calazans, Fabiano Hessel:
A Heterogeneous and Distributed Co-Simulation Environment. SBCCI 2002: 115-120 - [c4]José Carlos S. Palma, Aline Vieira de Mello, Leandro Möller, Fernando Moraes, Ney Calazans:
Core Communication Interface for FPGAs. SBCCI 2002: 183-190 - [c3]César Augusto Missio Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Requirements, Primitives and Models for Systems Specification. SBCCI 2002: 323-330 - 2001
- [j2]Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli:
Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8(1): 23-41 (2001) - [j1]Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. IEEE Trans. Educ. 44(2): 109-119 (2001) - [c2]Fernando Moraes, Alexandre M. Amory, Ney Calazans, Eduardo Bezerra, Juracy Petrini:
Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto. SBCCI 2001: 38-43
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last updated on 2024-08-05 21:20 CEST by the dblp team
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