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Cheng-Kok Koh
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Publications
- 2010
- [j23]Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy:
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1621-1624 (2010) - 2009
- [j21]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1749-1752 (2009) - 2006
- [c65]Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163 - 2005
- [j11]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) - [j10]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 75-85 (2005) - [c54]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. CICC 2005: 775-778 - [c51]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118 - 2004
- [c49]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898 - 2003
- [j9]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1521-1532 (2003) - [c42]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A metric for analyzing effective on-chip inductive coupling. ASP-DAC 2003: 156-161 - [c41]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823 - [c40]Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731 - [c35]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234 - 2002
- [j8]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 81-92 (2002) - [c31]Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy:
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935 - [c30]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346 - [c28]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234 - [c25]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ASP-DAC/VLSI Design 2002: 489- - 2001
- [c23]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851 - [c21]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417 - [c20]Rui Wang, Kaushik Roy, Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889 - [c19]Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270 - [c18]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71 - [c17]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222 - [e1]Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, ISBN 1-58113-351-0 [contents] - 2000
- [c16]Liqiong Wei, Kaushik Roy, Cheng-Kok Koh:
Power minimization by simultaneous dual-Vth assignment and gate-sizing. CICC 2000: 413-416 - [c14]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213 - [c12]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411 - [c11]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492 - [c10]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72 - [c9]Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
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