"Integrated architectural/physical planning approach for minimization of ..."

Yiran Chen, Kaushik Roy, Cheng-Kok Koh (2003)

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DOI: 10.1145/871506.871563

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234

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