Ching-Te Chiu

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Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
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Publications

2024
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Yi-Fan Chen, Yu-Jen Chang, Ching-Te Chiu, Ming-Long Huang, Geng-Ming Liang, Chao-Lin Lee, Jenq-Kuen Lee, Ping-Yu Hsieh, Wei-Chih Lai:
Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. ISCAS 2024: 1-5
[c85]
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An-Ting Hsieh, Ching-Te Chiu, Tsai-Chieh Chen, Mao-Hsiu Hsu, Wenyong Long:
Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition. ISCAS 2024: 1-5
2023
[j29]
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  - journals/access/ChengCKSLLCLCCH23
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Chih-Han Cheng, Ching-Te Chiu, Chia-Yu Kuan, Yu-Chi Su, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho:
Multiple Training Stage Image Enhancement Enrolled With CCRGAN Pseudo Templates for Large Area Dry Fingerprint Recognition. IEEE Access 11: 86790-86800 (2023)
[j28]
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Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang:
EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. J. Signal Process. Syst. 95(5): 657-669 (2023)
[c84]
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  - conf/aicas/ChenCL23
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Wei-Jyun Chen, Ching-Te Chiu, Ting-Chun Lin:
Landmark-Based Adversarial Network for RGB-D Pose Invariant Face Recognition. AICAS 2023: 1-5
[c83]
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Yu-Chi Su, Ching-Te Chiu, Chih-Han Cheng, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho:
CPGAN: Collective Punishment Generative Adversarial Network for Dry Fingerprint Image Enhancement. AICAS 2023: 1-5
[c82]
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  - conf/apsipa/HuangCC23
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Shi-Zong Huang, Ching-Te Chiu, Yu-Jen Chang:
Machine Learning Based Action Recognition with Modular CNN. APSIPA ASC 2023: 211-216
[c81]
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  - conf/icassp/LinCS23
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Wei-Chen Lin, Ching-Te Chiu, Kuan-Chang Shih:
RGB-D Based Pose-Invariant Face Recognition Via Attention Decomposition Module. ICASSP 2023: 1-5
[c80]
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  - conf/newcas/KuoCH23
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Hsueh-Kai Kuo, Ching-Te Chiu, Lien-Chieh Huang:
Low Temperature and Dry Fingerprint Restoration with Ridge Loss and Orientation. NEWCAS 2023: 1-5
[c79]
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Shu-Yun Wu, Ching-Te Chiu, Yung-Ching Hsu:
Pose Aware RGBD-based Face Recognition System With Hierarchical Bilinear Pooling. NEWCAS 2023: 1-5
[i2]
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  - journals/corr/abs-2308-07024
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Yu-Ting Li, Ching-Te Chiu, An-Ting Hsieh, Mao-Hsiu Hsu, Wenyong Long, Jui-Min Hsu:
PGT-Net: Progressive Guided Multi-task Neural Network for Small-area Wet Fingerprint Denoising and Recognition. CoRR abs/2308.07024 (2023)
2022
[j27]
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Ching-Te Chiu, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, Yuan-Hao Huang:
Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4847-4859 (2022)
[c78]
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Jheng-Yi Chang, Ching-Te Chiu, Pin-Hsuan Chen:
Lightweight and Efficient Neural Network Using Progressively Greedy Search. AICAS 2022: 46-49
[c77]
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  - conf/iscas/ChengCC22
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Yen-Yu Cheng, Ching-Te Chiu, Yi-Fan Chen:
RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module. ISCAS 2022: 2715-2719
[c76]
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  - conf/iscas/LuoCH22
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Jie-Yu Luo, Ching-Te Chiu, An-Ting Hsieh:
Multi-View RGB-D Based 3D Point Cloud Face Model Reconstruction System. ISCAS 2022: 3008-3012
2021
[j26]
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Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, Hsueh-Kai Kuo:
Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4182-4193 (2021)
[j25]
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Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng:
Object Detection in RGB-D Images via Anchor Box with Multi-Reduced Region Proposal Network and Multi-Pooling. J. Signal Process. Syst. 93(10): 1219-1233 (2021)
[c75]
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  - conf/apsipa/PuCW21
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Yen-Yu Pu, Ching-Te Chiu, Shu-Yun Wu:
Real-Time Edge Attention-Based Learning for Low-Light One-Stage Object Detection. APSIPA ASC 2021: 1483-1487
[c74]
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  - conf/apsipa/TangCC21
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Ching-Tung Tang, Ching-Te Chiu, Wei-Jyun Chen:
3D Landmark-based Face Detection and Recognition System for Large Poses. APSIPA ASC 2021: 2055-2059
[c73]
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  - conf/csci/HsiaoC21
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Shan-Chien Hsiao, Ching-Te Chiu:
Efficient 2D Keypoint-based Hand Pose Estimation. CSCI 2021: 1648-1652
[c72]
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Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shan-Chien Hsiao:
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. ISCAS 2021: 1-5
2020
[j23]
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  - journals/jsa/HsuCLCP20
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Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin, Hsing-Huan Chou, Yen-Yu Pu:
ESSA: An energy-Aware bit-Serial streaming deep convolutional neural network accelerator. J. Syst. Archit. 111: 101831 (2020)
[j22]
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  - journals/tnn/ShihCLB20
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Kuan-Hung Shih, Ching-Te Chiu, Jiou-Ai Lin, Yen-Yu Bu:
Real-Time Object Detection With Reduced Region Proposal Network via Multi-Feature Concatenation. IEEE Trans. Neural Networks Learn. Syst. 31(6): 2164-2173 (2020)
[j21]
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Yung-Chang Chang, Cihun-Siyong Alex Gong, Ching-Te Chiu:
Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy. J. Signal Process. Syst. 92(4): 345-355 (2020)
[c70]
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  - conf/icassp/WangCHDW20
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Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang:
Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. ICASSP 2020: 1568-1572
[c69]
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  - conf/icassp/LoCL20
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Wen-Yi Lo, Ching-Te Chiu, Jie-Yu Luo:
Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor. ICASSP 2020: 1613-1617
[c68]
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Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng:
Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling. ICASSP 2020: 1618-1622
[c67]
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  - conf/icassp/HsuCK20
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Chia-Ho Hsu, Ching-Te Chiu, Chia-Yu Kuan:
Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network. ICASSP 2020: 1653-1657
[c66]
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  - conf/icassp/LinCT20
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Tzu-Ying Lin, Ching-Te Chiu, Ching-Tung Tang:
Rgb-D Based Multi-Modal Deep Learning for Face Identification. ICASSP 2020: 1668-1672
[c65]
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  - conf/sips/LiCH20
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Kuang-Chien Li, Ching-Te Chiu, Shan-Chien Hsiao:
Semantic Segmentation via Enhancing Context Information by Fusing Multiple High-Level Features. SiPS 2020: 1-5
[i1]
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  - journals/corr/abs-2009-07409
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Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang:
EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. CoRR abs/2009.07409 (2020)
2019
[j20]
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Ting-Yun Hsiao, Yung-Chang Chang, Hsin-Hung Chou, Ching-Te Chiu:
Filter-based deep-compression with global average pooling for convolutional networks. J. Syst. Archit. 95: 9-18 (2019)
[c64]
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  - conf/icassp/ShihCP19
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Kuan-Hung Shih, Ching-Te Chiu, Yen-Yu Pu:
Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network. ICASSP 2019: 1398-1402
[c62]
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Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin:
An Energy-Aware Bit-Serial Streaming Deep Convolutional Neural Network Accelerator. ICIP 2019: 4609-4613
2018
[j19]
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Jen-Wen Wang, Ching-Te Chiu:
Video Super-resolution using Edge-based Optical Flow and Intensity Prediction. J. Signal Process. Syst. 90(12): 1699-1711 (2018)
[c59]
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Ting-Yun Hsiao, Yung-Chang Chang, Ching-Te Chiu:
Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks. SiPS 2018: 247-251
2016
[c53]
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  - conf/icassp/ChuC16
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Tsai-Te Chu, Ching-Te Chiu:
A cost-effective minutiae disk code for fingerprint recognition and its implementation. ICASSP 2016: 981-985
[c51]
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  - conf/iscas/WuCH16
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Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu:
Binary descriptor based SIFT and hardware implementation. ISCAS 2016: 610-613
2015
[j17]
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Tsun-Hsien Wang, Cheng-Wen Chiu, Wei-Chen Wu, Jen-Wen Wang, Chun-Yi Lin, Ching-Te Chiu, Jing-Jia Liou:
Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. IEEE Trans. Multim. 17(4): 470-484 (2015)
[j15]
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Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu:
Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling. J. Signal Process. Syst. 78(1): 95-113 (2015)
[c50]
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Tsun-Hsien Wang, Jen-Wen Wang, Ching-Te Chiu:
Virtual HDR/LDR image synthesizer in multi-core platform. GlobalSIP 2015: 619-623
[c48]
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  - conf/iscas/TsaiHCC15
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Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu:
Accelerating AdaBoost algorithm using GPU for multi-object recognition. ISCAS 2015: 738-741
2014
[j14]
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Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Shawn S. H. Hsu, Mau-Chung Frank Chang:
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3278-3287 (2014)
[c46]
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Loyon Kuo, Tsun-Hsien Wang, Ching-Te Chiu:
Gradient-based image up-scaling with local self similarity. GlobalSIP 2014: 960-964
[c45]
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Jen-Wen Wang, Ching-Te Chiu:
Edge-based motion and intensity prediction for video super-resolution. GlobalSIP 2014: 1039-1043
[c43]
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  - conf/icce-tw/WuCH14
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Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu:
Object recognition using bag of words with kernels for big data. ICCE-TW 2014: 89-90
[c42]
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  - conf/vlsi-dat/ChangHLYC14
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Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu:
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. VLSI-DAT 2014: 1-4
2013
[j13]
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  - journals/tvlsi/ChiuHLWHLCKH13
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Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu:
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1481-1495 (2013)
[j12]
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Ching-Te Chiu, Wen-Chih Huang, Chih-Hsing Lin, Wei-Chih Lai, Ying-Fang Tsao:
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1797-1810 (2013)
[j11]
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Wei-Chih Lai, Ching-Te Chiu:
Data Center Switch for Load Balanced Fat-Trees. J. Signal Process. Syst. 71(3): 173-187 (2013)
[c40]
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  - conf/apsipa/TsaoLC13
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Ying-Fang Tsao, Wen-Te Liu, Ching-Te Chiu:
Human gait analysis by body segmentation and center of gravity. APSIPA 2013: 1-5
[c38]
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  - conf/icip/WuWC13
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Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu:
Edge curve scaling and smoothing with cubic spline interpolation. ICIP 2013: 859-862
[c37]
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Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu:
Edge curve scaling and smoothing with cubic spline interpolation for image upscaling. SiPS 2013: 65-70
2012
[j10]
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Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu:
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2600-2610 (2012)
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Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu:
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. J. Signal Process. Syst. 66(1): 57-73 (2012)
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Yung-Chang Chang, Ching-Te Chiu:
A Study of NoC Topologies and Switching Arbitration Mechanisms. HPCC-ICESS 2012: 1643-1647
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Wei-Chih Lai, Ching-Te Chiu:
A 5.8 Gbps uniform mapping data center switch. ICASSP 2012: 1577-1580
[c34]
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Wei-Chiu Liu, Zhan-Yao Gu, Yarsun Hsu, Ching-Te Chiu:
Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks. ICCVE 2012: 43-48
[c33]
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Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao:
A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ISCAS 2012: 245-248
2011
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Wei-Ming Ke, Chih-Rung Chen, Ching-Te Chiu:
BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement. IEEE Trans. Circuits Syst. Video Technol. 21(3): 360-364 (2011)
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Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu:
A 0.64 mm ² Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1937-1948 (2011)
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Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu:
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. 64(1): 93-107 (2011)
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Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu:
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC 2011: 105-106
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Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu:
On the design and analysis of fault tolerant NoC architecture using spare routers. ASP-DAC 2011: 431-436
[c29]
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Chih-Rung Chen, Ching-Te Chiu:
Curve-based and image-based JND contrast analysis for inverse tone mapping operators. ICIP 2011: 345-348
[c28]
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Tsun-Hsien Wang, Ching-Te Chiu:
Low visual difference virtual high dynamic range image synthesizer from a single legacy image. ICIP 2011: 2265-2268
[c27]
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Ching-Te Chiu, Cyuan-Jhe Wu:
Texture classification based low order local binary pattern for face recognition. ICIP 2011: 3017-3020
[c26]
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Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu:
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. ISCAS 2011: 185-188
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Wen-Chih Huang, Chih-Hsing Lin, Ching-Te Chiu:
Embedded transition inversion coding for low power serial link. SiPS 2011: 102-105
2010
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Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu:
Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal. IEEE Trans. Image Process. 19(9): 2307-2320 (2010)
[c23]
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Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu:
Switching bilateral filter with a texture/noise detector for universal noise removal. ICASSP 2010: 1434-1437
[c22]
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Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu:
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS 2010: 581-584
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Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen:
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. ISCAS 2010: 1061-1064
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Wei-Ming Ke, Ching-Te Chiu:
Hardware-efficient image enhancement with bilateral tone adjustment. ISCAS 2010: 3365-3368
[c19]
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Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A novel MUX-FF circuit for low power and high speed serial link interfaces. ISCAS 2010: 4305-4308
2009
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Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu:
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 688-696 (2009)
[c18]
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Wei-Ming Ke, Tsun-Hsien Wang, Ching-Te Chiu:
Hardware-efficient virtual high dynamic range image reproduction. ICIP 2009: 2693-2696
[c17]
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Wei-Su Wong, Chih-Rung Chen, Ching-Te Chiu:
A 100MHz hardware-efficient boost cascaded face detection design. ICIP 2009: 3237-3240
2008
[c16]
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Chih-Hsing Lin, Ching-Te Chiu:
A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias. ICECS 2008: 790-793
[c15]
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Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay:
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. ICIP 2008: 1400-1403
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Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. ISCAS 2008: 3086-3089
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Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay:
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. SiPS 2008: 25-30
2007
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Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu:
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. ASP-DAC 2007: 102-103
[c11]
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Tsun-Hsien Wang, Wei-Su Wong, Fang-Chu Chen, Ching-Te Chiu:
Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video. ICIP (6) 2007: 209-212
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Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao, Fang-Chu Chen, Ching-Te Chiu:
Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications. ICIP (3) 2007: 561-564
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Tsun-Hsien Wang, Ching-Te Chiu:
Low Power Design of High Performance Memory Access Architecture for HDTV Decoder. ICME 2007: 699-702
[c8]
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Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ISCAS 2007: 2754-2757
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Chih-Hsing Lin, Ching-Te Chiu:
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. ISCAS 2007: 3888-3891
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Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu:
Design of ultra low power CML MUXs and latches with forward body bias. SoCC 2007: 141-144
2006
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Hou-Cheng Tzeng, Ching-Te Chiu:
A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS. NCA 2006: 243-246
2005
[c4]
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Chih-Ying Tu, Cheng-Shang Chang, Duan-Shin Lee, Ching-Te Chiu:
Design a simple and high performance switch using a two-stage architecture. GLOBECOM 2005: 6
[c3]
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Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng:
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. IWSOC 2005: 508-513
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Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu:
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. SoCC 2005: 257-260

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