Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Tadashi Shibata
2010 – today
- 2013
[j14]Ruihan Bao, Tadashi Shibata: A hardware friendly algorithm for action recognition using spatio-temporal motion-field patches. Neurocomputing 100: 98-106 (2013)- [j13]Pushe Zhao, Hongbo Zhu, He Li, Tadashi Shibata: A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation. IEEE Trans. Circuits Syst. Video Techn. 23(3): 503-517 (2013)
- 2012
- [c47]Renyuan Zhang, Tadashi Shibata: Real-Time On-Line-Learning Support Vector Machine Based on a Fully-Parallel Analog VLSI Processor. ICAISC (2) 2012: 223-230
- [c46]Ruihan Bao, Tadashi Shibata: A Hierarchical Action Recognition System Applying Fisher Discrimination Dictionary Learning via Sparse Representation. ICAISC (1) 2012: 468-476
- [c45]Pushe Zhao, Renyuan Zhang, Tadashi Shibata: Real-Time Object Tracking Algorithm Employing On-Line Support Vector Machine and Multiple Candidate Regeneration. ICAISC (1) 2012: 617-625
- [c44]Shigetaka Morikawa, Tadashi Shibata: Scene image recognition based on the sequence of local image vectors represented by oriented edges. ICASSP 2012: 1313-1316
- [c43]Hongbo Zhu, Tadashi Shibata: A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture. ISCAS 2012: 1612-1615
- [c42]Wenjun Xia, Tadashi Shibata: Self-adaptive quasi-Gaussian circuits for analog on-chip-trainable multi-class classifiers. ISCAS 2012: 2893-2896
- 2011
- [c41]Wenjun Xia, Tadashi Shibata: Critical Boundary Vector Concept in Nearest Neighbor Classifiers using k-Means Centers for Efficient Template Reduction. IJCCI (NCTA) 2011: 93-98
- 2010
- [j12]Hitoshi Hayakawa, Tadashi Shibata: Block-matching-based motion field generation utilizing directional edge displacement. Computers & Electrical Engineering 36(4): 617-625 (2010)
- [j11]Jia Hao, Tadashi Shibata: An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations. IEICE Transactions 93-D(1): 94-106 (2010)
- [j10]Jun Chen, Tadashi Shibata: A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation. IEEE Trans. on Circuits and Systems 57-I(6): 1143-1153 (2010)
- [j9]Kyunghee Kang, Tadashi Shibata: An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine. IEEE Trans. on Circuits and Systems 57-I(7): 1513-1524 (2010)
- [c40]Trong Tu Bui, Tadashi Shibata: A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques. DELTA 2010: 54-57
- [c39]Norihiro Takahashi, Tadashi Shibata: A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation. ISCAS 2010: 625-628
- [c38]Zhuoli Sun, Kyunghee Kang, Tadashi Shibata: A self-learning multiple-class classifier using multi-dimensional quasi-Gaussian analog circuits. ISCAS 2010: 2330-2333
- [c37]Hongbo Zhu, Pushe Zhao, Tadashi Shibata: Directional-edge-based object tracking employing on-line learning and regeneration of multiple candidate locations. ISCAS 2010: 2630-2633
2000 – 2009
- 2009
- [j8]Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata: A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter. Integration 42(2): 254-261 (2009)
- [j7]Kiyoto Ito, Benjamas Tongprasit, Tadashi Shibata: A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing. IEEE Trans. on Circuits and Systems 56-I(1): 114-123 (2009)
- [j6]Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata: A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors. IEEE Trans. on Circuits and Systems 56-I(11): 2384-2392 (2009)
- [c36]Norihiro Takahashi, Tadashi Shibata: A Non-subtraction Configuration of Self-similitude Architecture for Multiple-Resolution Edge-Filtering CMOS Image Sensor. ICANN (1) 2009: 391-400
- [c35]Mio Nishiyama, Tadashi Shibata: Normalized scoring of Hidden Markov Models by on-line learning and its application to gesture-sequence perception. ICIP 2009: 3565-3568
- [c34]Yudai Fukuoka, Tadashi Shibata: Block-matching-based CMOS Optical Flow Sensor using Only-nearest-neighbor Computation. ISCAS 2009: 1485-1488
- [c33]Kyunghee Kang, Tadashi Shibata: An On-chip-trainable Gaussian-kernel Analog Support Vector Machine. ISCAS 2009: 2661-2664
- [c32]Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata: A Single-motion-vector/Cycle-generation Optical Flow Processor Employing Directional-edge Histogram Matching. ISCAS 2009: 3022-3025
- [c31]Takuki Nakagawa, Tadashi Shibata: A Real-time Image Feature Vector Generator Employing Functional Cache Memory for Edge Flags. ISCAS 2009: 3026-3029
- 2008
- [j5]Tadashi Shibata: Special Section on Advanced Processors Based on Novel Concepts in Computation. IEICE Transactions 91-C(9): 1385 (2008)
- [c30]Robert Grou-Szabo, Tadashi Shibata: Blind image compression history determination using dynamic thresholding. ICASSP 2008: 1005-1008
- [c29]Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata: An analog self-similitude edge-filtering processor for multiple-resolution image perception. ISCAS 2008: 1640-1643
- [c28]Hitoshi Hayakawa, Tadashi Shibata: Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception. ISCAS 2008: 3526-3529
- 2006
- [c27]Kiyoto Ito, Tadashi Shibata: A time-domain gradient-detection architecture for VLSI analog motion sensors. ISCAS 2006
- [c26]Benjamas Tongprasit, Tadashi Shibata: Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. ISCAS 2006
- 2005
- [c25]Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata: A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. ISCAS (3) 2005: 2389-2392
- [c24]Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata: A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. ISCAS (6) 2005: 5365-5368
- [c23]Yusuke Nakashita, Yoshio Mita, Tadashi Shibata: An Analog Visual Pre-Processing Processor. NIPS 2005
- 2004
- [c22]Hideo Yamasaki, Tadashi Shibata: A real-time VLSI median filter employing two-dimensional bit-propagating architecture. ISCAS (2) 2004: 349-352
- [c21]Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata: Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. ISCAS (1) 2004: 425-428
- [c20]Masayuki Umejima, Toshihiko Yamasaki, Tadashi Shibata: A bump-circuit-based motion detector using projected-activity histograms. ISCAS (1) 2004: 749-752
- 2003
- [j4]Bernabé Linares-Barranco, Andreas G. Andreou, Giacomo Indiveri, Tadashi Shibata: Guest editorial - Special issue on neural networks hardware implementations. IEEE Transactions on Neural Networks 14(5): 976-979 (2003)
- [j3]Masakazu Yagi, Tadashi Shibata: An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems. IEEE Transactions on Neural Networks 14(5): 1144-1161 (2003)
- [j2]Toshihiko Yamasaki, Tadashi Shibata: Analog soft-pattern-matching classifier using floating-gate MOS technology. IEEE Transactions on Neural Networks 14(5): 1257-1265 (2003)
- [c19]Shantanu Chakrabartty, Masakazu Yagi, Tadashi Shibata, Gert Cauwenberghs: Robust cephalometric landmark identification using support vector machines. ICME 2003: 429-432
- [c18]Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata: A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors. NIPS 2003
- [c17]Masakazu Yagi, Tadashi Shibata, Chihiro Tanikawa, Kenji Takada: A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation. SCIA 2003: 534-540
- 2002
- [c16]Masakazu Yagi, Tadashi Shibata: A human-perception-like image recognition system based on PAP vector representation with multi resolution concept. ICASSP 2002: 1045-1048
- [c15]Masakazu Yagi, Tadashi Shibata: An associative-processor-based mixed signal system for robust grayscale image recognition. ISCAS (5) 2002: 137-140
- [c14]Hiroe Kimura, Tadashi Shibata: A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm. ISCAS (3) 2002: 333-336
- [c13]Toshihiko Yamasaki, T. Taguchi, Tadashi Shibata: Low-power CDMA analog matched filters based on floating-gate technology. ISCAS (5) 2002: 625-628
- [c12]Keng Hoong Wee, T. Yonezawa, Toshiyuki Nozawa, Tadashi Shibata, Tadahiro Ohmi: A zone-programmed EEPROM with real-time write monitoring for analog data storage. ISCAS (4) 2002: 655-658
- [c11]Huaiyu Xu, Yoshio Mita, Tadashi Shibata: Intelligent Internet Search Applications Based on VLSI Associative Processors. SAINT 2002: 230-237
- 2001
- [c10]Keng Hoong Wee, Toshiyuki Nozawa, T. Yonezawa, Y. Yamashita, Tadashi Shibata, Tadahiro Ohmi: High-precision analog EEPROM with real-time write monitoring. ISCAS (1) 2001: 105-108
- [c9]Toshihiko Yamasaki, Tadashi Shibata: An analog similarity evaluation circuit featuring variable functional forms. ISCAS (3) 2001: 561-564
- [c8]Toshihiko Yamasaki, A. Suzuki, D. Kobayashi, Tadashi Shibata: A fast self-convergent flash-memory programming scheme for MV and analog data storage. ISCAS (4) 2001: 930-933
- [c7]Toshihiko Yamasaki, Tadashi Shibata: Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology. NIPS 2001: 1131-1138
1990 – 1999
- 1999
- [j1]Tadahiro Ohmi, Tadashi Shibata, Koji Kotani, Tsutomu Nakai, Akira Nakada, Ning Mei Yu, Masahiro Konda, Tatsuo Morimoto, Yuichiro Yamashita: Association hardware for intelligent electronic systems. Systems and Computers in Japan 30(12): 52-62 (1999)
- [c6]Atsuhiko Okada, Tadashi Shibata: A neuron-MOS parallel associator for high-speed CDMA matched filter. ISCAS (2) 1999: 392-395
- 1998
- [c5]
- [c4]Tadashi Shibata: Right brain computing hardware: a psychological brain model on silicon. KES (3) 1998: 429-435
- [c3]Tatsuo Morimoto, Tadashi Shibata, Tadahiro Ohmi: Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing. KES (3) 1998: 436-441
- 1995
- [c2]Tadashi Shibata, Tsutomu Nakai, Tatsuo Morimoto, Ryu Kaihara, Takeo Yamashita, Tadahiro Ohmi: Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. NIPS 1995: 685-691
- 1993
- [c1]Tadashi Shibata, Koji Kotani, Takeo Yamashita, Hiroshi Ishii, Hideo Kosaka, Tadahiro Ohmi: Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. NIPS 1993: 919-926
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-03-14 00:20 CET by the dblp team