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IEEE Transactions on Very Large Scale Integration Systems, Volume 32
Volume 32, Number 1, January 2024
- Jari Nurmi, Snorre Aunet, Alireza Saberkari:
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. 1-3 - Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan:
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters. 4-15 - Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
HW-FUTEX: Hardware-Assisted Futex Syscall. 16-29 - Christian Lanius, Tobias Gemmeke:
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing. 30-41 - Siavash Mowlavi, Stavros Giannakopoulos, Alexander Grabowski, Lars Svensson:
A Review of IC Drivers for VCSELs in Datacom Applications. 42-54 - Yu-Kai Huang, Saul Rodriguez:
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications. 55-67 - Johnson Loh, Tobias Gemmeke:
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers. 68-78 - Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal:
Design and Analysis of the Leapfrog Control-Bounded A/D Converter. 79-88 - Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho:
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. 89-102 - Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou:
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. 103-115 - Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. 116-127 - Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou:
Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications. 128-136 - Pengcheng Huang, Yaohua Wang, Zhenyu Zhao, Daheng Yue:
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. 137-149 - Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø:
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. 150-163 - Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei:
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. 164-177 - Chenghan Wang, Qinzhi Xu, Chuanjun Nie, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li:
A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System. 178-189 - Shourya Gupta, Shuo Li, Benton H. Calhoun:
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. 190-194 - Irith Pomeranz:
Testability Evaluation for Local Design Modifications. 195-199 - Ke Chang, Qian Xing, Guoliang Jia, Yang Pu, Yan Wang, Yuxin Wang, Yanlong Zhang, Guohe Zhang:
An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ. 200-204
Volume 32, Number 2, February 2024
- Lucas Compassi Severo, Tailize C. De-Oliveira, Paulo César Comassetto de Aguirre, Wilhelmus A. M. Van Noije, Alessandro Gonçalves Girardi:
Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters. 205-218 - Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis:
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design. 219-230 - Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl:
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. 231-244 - Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo:
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. 245-255 - Liang Chang, Xin Zhao, Ting Yue, Xi Yang, Chenglong Li, Shuisheng Lin, Jun Zhou:
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro. 256-268 - Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen:
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. 269-282 - Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou:
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. 283-290 - Bin Li, Yunfei Yan, Yuanxin Wei, Heru Han:
Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA. 291-304 - Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi:
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. 305-318 - Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi:
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel. 319-332 - Md. Moshiur Rahman, Swarup Bhunia:
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection. 333-346 - Christopher Vega, Patanjali SLPSK, Swarup Bhunia:
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks. 347-360 - Vijaypal Singh Rathor, Munesh Singh, Kshira Sagar Sahoo, Saraju P. Mohanty:
GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking. 361-371 - Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding:
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques. 372-381 - Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, Hongshuo Li, Weijiang Wang:
High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm. 382-395 - Run Yan, Yin Su, Hui Guo, Yashuai Lü, Jin Wang, Nong Xiao, Li Shen, Yongwen Wang, Libo Huang:
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing. 396-400
Volume 32, Number 3, March 2024
- Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim:
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping. 401-412 - Sai Pentapati, Sung Kyu Lim:
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs. 413-421 - Xiaoxiao Zheng, Mao Ye, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao:
A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR. 422-431 - Hongge Li, Yuhao Chen:
Hybrid Stochastic Number and Its Neural Network Computation. 432-441 - Yongqiang Zhang, Jiao Qin, Jie Han, Guangjun Xie:
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm. 442-454 - Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar:
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. 455-467 - Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi:
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. 468-479 - Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu:
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. 480-484 - Zhaojun Lu, Xueyan Wang, Md Tanvir Arafin, Haoxiang Yang, Zhenglin Liu, Jiliang Zhang, Gang Qu:
An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference. 485-496 - YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, Xiangshui Miao:
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. 497-504 - Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang:
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. 505-518 - Si-Huang Liu, Chia-Yi Kuo, Yannan Mo, Tao Su:
An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT. 519-529 - Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji:
A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS. 530-541 - Yifei Zheng, Boyu Li, Qianheng Dong, Yutao Ying, Deyuan Song, Jing Zhu, Weifeng Sun, Qinsong Qian, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou:
A 200-V Half-Bridge Monolithic GaN Power IC With High-Speed Level Shifter and dVS/dt Noise Immunity Enhancement Structure. 542-551 - Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi:
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. 552-563 - Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara:
A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. 564-572 - Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. 573-586 - Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu:
An Open-Loop VCO-ADC Based on a Linearized Current Control Technique. 587-591 - Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs. 592-596
Volume 32, Number 4, April 2024
- Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. 597-608 - Irith Pomeranz:
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. 609-618 - Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar:
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. 619-632 - Erfan Bank Tavakoli, Michael Riera, Masudul Hassan Quraishi, Fengbo Ren:
FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs. 633-644 - Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. 645-657 - Musha Ji'e, Hongxin Peng, Shukai Duan, Lidan Wang, Fengqing Zhang, Dengwei Yan:
Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium. 658-668 - Jia-Zhao Lin, Po-Ta Chen, Hung-Yuan Chin, Pei-Yun Tsai, Sz-Yuan Lee:
Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability. 669-681 - Basant Kumar Mohanty:
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors. 695-703 - Yi-Hao Lan, Shen-Iuan Liu:
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. 704-713 - Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang:
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber. 714-727 - Ana Mitrovic, Eby G. Friedman:
Thermal Exploration of RSFQ Integrated Circuits. 728-738 - Joseph Franklin Clements, Yingjie Lao:
Reliable Hardware Watermarks for Deep Learning Systems. 752-762 - Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui C. V. Loureiro, Shufan Yang, Hubin Zhao:
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection. 763-773 - Jun Liu, Songren Cheng, Tian Chen, Xi Wu, Huaguo Liang:
A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution. 774-781 - Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du:
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction. 782-786 - Hsi-Kai Peng, Shen-Iuan Liu:
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. 787-791
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