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2020 – today
- 2024
[j62]Trong-Hung Nguyen
, Binh Kieu-Do-Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium. IEEE Access 12: 34918-34930 (2024)- [j61]Phuc-Phan Duong, Hieu Minh Nguyen, Ba-Anh Dao, Binh Kieu-Do-Nguyen, Thai-Ha Tran, Trong-Thuc Hoang, Cong-Kha Pham:
Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps. IEEE Access 12: 63976-63994 (2024) - [j60]Ta Viet Tai, Ma Pham Nhut Tan, Duong Hoang Tien, Nguyen Viet Ha, Trong-Thuc Hoang, Cong-Kha Pham, Tran Thi Thao Nguyen:
A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis. IEEE Access 12: 70184-70197 (2024) - [j59]Tuan-Kiet Dang, Khai-Duy Nguyen, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham:
Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications. Future Internet 16(5): 157 (2024) - [j58]Binh Kieu-Do-Nguyen, Nguyen The Binh, Cuong Pham-Quoc, Huynh Phuc Nghi, Ngoc-Thinh Tran, Trong-Thuc Hoang, Cong-Kha Pham:
Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme. Inf. 15(7): 400 (2024) - [j57]Tuan-Kiet Dang, Khai-Duy Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3543-3547 (2024) - [j56]Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 573-586 (2024) - [c69]Binh Kieu-Do-Nguyen, Khai-Duy Nguyen, Tuan-Kiet Dang, Cong-Kha Pham, Trong-Thuc Hoang:
A Trusted Execution Environment RISC-V System on Chip. HCS 2024: 1 - [c68]Khai-Duy Nguyen, Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
RISC-V-Based System-on-Chips for IoT Applications. HCS 2024: 1 - [c67]Nhu-Hoang Nguyen, Tan-Phat Dang, Thanh-Dat Bui, Trong-Thuc Hoang, Cong-Kha Pham, Huu-Thuan Huynh:
Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding. ICCSA (Workshops 1) 2024: 110-121 - [c66]Phuc-Phan Duong, Trong-Thuc Hoang, Cong-Kha Pham:
A Strong 4 × 4 S-Box Using an Enhanced Tent Map. ISCAS 2024: 1-5 - [c65]Trong-Hung Nguyen, Nguyen The Binh, Huynh Phuc Nghi, Cong-Kha Pham, Trong-Thuc Hoang:
Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems. ISCAS 2024: 1-5 - [c64]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham:
A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS 2024: 1-5 - [c63]Thai-Ha Tran, Van-Phuc Hoang, Duc-Hung Le, Trong-Thuc Hoang, Cong-Kha Pham:
An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode. ISCAS 2024: 1-5 - 2023
- [j55]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang:
Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor. IEEE Access 11: 4879-4894 (2023) - [j54]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment. Comput. Electr. Eng. 105: 108546 (2023) - [j53]Duc-Thuan Dam, Thai-Ha Tran, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
A Survey of Post-Quantum Cryptography: Start of a New Race. Cryptogr. 7(3): 40 (2023) - [j52]Trong-Hung Nguyen, Cong-Kha Pham, Trong-Thuc Hoang:
A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography. Cryptogr. 7(4): 46 (2023) - [j51]Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang:
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. Future Internet 15(5): 186 (2023) - [j50]Ngoc-Tuan Do, Van-Phuc Hoang, Van-Sang Doan, Cong-Kha Pham:
On the performance of non-profiled side channel attacks based on deep learning techniques. IET Inf. Secur. 17(3): 377-393 (2023) - [j49]Trung Dinh Pham, Cuong Pham-Quoc, Tran Ngoc Thinh, Binh Kieu-Do-Nguyen, Cong-Kha Pham:
A flexible and efficient FPGA-based random forest architecture for IoT applications. Internet Things 22: 100813 (2023) - [j48]Hong-Hai Thai, Cong-Kha Pham, Duc-Hung Le:
Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process. Sensors 23(1): 76 (2023) - [j47]Thai-Ha Tran, Ba-Anh Dao, Trong-Thuc Hoang, Van-Phuc Hoang, Cong-Kha Pham:
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC. IEEE Trans. Computers 72(9): 2689-2700 (2023) - [c62]Thai-Ha Tran, Anh-Tien Le, Trong-Thuc Hoang, Van-Phuc Hoang, Cong-Kha Pham:
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks. ACM Great Lakes Symposium on VLSI 2023: 439-442 - [c61]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham:
In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. ISCAS 2023: 1-5 - [c60]Van-Phuc Hoang, Ngoc-Tuan Do, Trong-Thuc Hoang, Cong-Kha Pham:
Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks. MCSoC 2023: 9-14 - [c59]Nguyen The Binh, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham, Cuong Pham-Quoc:
FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V. RIVF 2023: 31-36 - 2022
- [j46]Ngoc-Tuan Do, Van-Phuc Hoang, Cong-Kha Pham:
Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques. IEEE Access 10: 17578-17589 (2022) - [j45]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. IEEE Access 10: 41852-41862 (2022) - [j44]Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. IEEE Access 10: 46014-46027 (2022) - [j43]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Cong-Kha Pham:
A Unified NVRAM and TRNG in Standard CMOS Technology. IEEE Access 10: 79213-79221 (2022) - [j42]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang:
Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA. Cryptogr. 6(2): 25 (2022) - [j41]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Cong-Kha Pham, Trong-Thuc Hoang:
ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. Cryptogr. 6(2): 30 (2022) - [j40]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham:
A Unified PUF and Crypto Core Exploiting the Metastability in Latches. Future Internet 14(10): 298 (2022) - [j39]Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Ronaldo Serrano, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2438-2442 (2022) - [c58]Bien-Cuong Nguyen, Cong-Kha Pham:
A Combined Blinding-Shuffling Online Template Attacks Countermeasure Based on Randomized Domain Montgomery Multiplication. ICCE 2022: 1-6 - [c57]Tuan-Kiet Dang, Khai-Duy Nguyen, Quynh Nguyen Quang Nhu, Trong-Thuc Hoang, Cong-Kha Pham:
A System-on-Chip for IoT Applications with 16-bit Tiny Processor. ICICDT 2022: 44-47 - [c56]Binh Kieu-Do-Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Katsumi Inoue, Toshinori Usugi, Masanori Odaka, Shuichi Kameyama, Cong-Kha Pham:
High-speed FPGA-based Design and Implementation of Text Search Processor. ICICDT 2022: 109-112 - [c55]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Spectre attack detection with Neutral Network on RISC-V processor. ISCAS 2022: 2467-2471 - [c54]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham:
A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. ISOCC 2022: 79-80 - [c53]Tuan-Kiet Dang, Ronaldo Serrano, Trong-Thuc Hoang, Cong-Kha Pham:
A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators. ISOCC 2022: 87-88 - [c52]Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
High-performance Multi-function HMAC-SHA2 FPGA Implementation. NEWCAS 2022: 30-34 - 2021
- [j38]Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks. IEEE Access 9: 24768-24786 (2021) - [j37]Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. IEEE Access 9: 105748-105755 (2021) - [j36]Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure. IEEE Access 9: 151993-152014 (2021) - [j35]Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor. IEEE Access 9: 164597-164612 (2021) - [j34]Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Khai-Duy Nguyen, Xuan-Tu Tran, Cong-Kha Pham:
A proposal for enhancing training speed in deep learning models based on memory activity survey. IEICE Electron. Express 18(15): 20210252 (2021) - [j33]Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Xuan-Tu Tran, Cong-Kha Pham:
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. IEICE Electron. Express 18(16): 20210266 (2021) - [j32]Trung Q. Duong, Van-Phuc Hoang, Cong-Kha Pham:
Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow. Mob. Networks Appl. 26(4): 1747-1749 (2021) - [j31]Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham:
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3182-3186 (2021) - [c51]Trong-Thuc Hoang, Ckristian Duran, Ronaldo Serrano, Marco Sarmiento, Khai-Duy Nguyen, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. HCS 2021: 1-16 - [c50]Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Cong-Kha Pham:
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip. HCS 2021: 1-13 - [c49]Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. ISOCC 2021: 17-18 - [c48]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC 2021: 375-376 - 2020
- [j30]Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Quick Boot of Trusted Execution Environment With Hardware Accelerators. IEEE Access 8: 74015-74023 (2020) - [j29]Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). IEICE Electron. Express 17(20): 20200282 (2020) - [j28]Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Hung K. Nguyen, Cong-Kha Pham:
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. EAI Endorsed Trans. Ind. Networks Intell. Syst. 7(22): e2 (2020) - [j27]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS. Microprocess. Microsystems 73: 102970 (2020) - [c47]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Cong-Kha Pham:
Hardware-assisted High-performance DNA Alignment System. ICIIT 2020: 45-50 - [c46]Trong-Thuc Hoang, Ckristian Duran, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. ISCAS 2020: 1-4 - [c45]Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, Cong-Kha Pham:
Heterogeneous Hardware-assisted Parallel Processing for BWA-MEM DNA Alignment. RIVF 2020: 1-7
2010 – 2019
- 2019
- [j26]Duc-Hung Le, Trong-Thuc Hoang, Cong-Kha Pham:
A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC. IEICE Electron. Express 16(10): 20190116 (2019) - [j25]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB. Microprocess. Microsystems 69: 112-117 (2019) - [j24]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 472-476 (2019) - [j23]Trong-Thuc Hoang, Xuan-Thuan Nguyen, Duc-Hung Le, Cong-Kha Pham:
Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1723-1727 (2019) - [c44]Bien-Cuong Nguyen, Cong-Kha Pham:
An Efficient Hardware Implementation of Radix-16 Montgomery Multiplication. GCCE 2019: 1121-1122 - [c43]Ngoc-Tu Bui, Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC. ICIT 2019: 835-840 - [c42]Takahiro Hosaka, Trong-Thuc Hoang, Van-Phuc Hoang, Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham:
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter. ISCAS 2019: 1 - [c41]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Ngoc-Tu Bui, Van-Phuc Hoang, Cong-Kha Pham:
A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS. ISCAS 2019: 1-4 - 2018
- [j22]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation. IEEE Access 6: 16046-16059 (2018) - [j21]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Cong-Kha Pham:
A CORDIC-based QR decomposition for MIMO signal detector. IEICE Electron. Express 15(5) (2018) - [j20]Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC. IEICE Electron. Express 15(10): 20180302 (2018) - [j19]Katsumi Inoue, Trong-Thuc Hoang, Cong-Kha Pham:
Frequent items counter based on binary decoders. IEICE Electron. Express 15(20): 20180808 (2018) - [j18]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
A High-Throughput Low-Energy Arithmetic Processor. IEICE Trans. Electron. 101-C(4): 281-284 (2018) - [j17]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
A Low-Power Hybrid Adaptive CORDIC. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 496-500 (2018) - [c40]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm. ASP-DAC 2018: 327-328 - [c39]Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham:
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. COOL CHIPS 2018: 1-3 - [c38]Han Le Duc, Van-Phuc Hoang, Duc Minh Nguyen, Cong-Kha Pham:
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands. ISCAS 2018: 1-4 - [c37]Trong-Thuc Hoang, Cong-Kha Pham, Duc-Hung Le:
High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC. ISCAS 2018: 1-5 - [c36]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS. ISCAS 2018: 1-4 - [c35]Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations. MCSoC 2018: 225-232 - [c34]Katsumi Inoue, Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study. PRIME 2018: 161-164 - [i5]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation. CoRR abs/1803.11207 (2018) - [i4]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
An Efficient I/O Architecture for RAM-based Content-Addressable Memory on FPGA. CoRR abs/1804.02330 (2018) - [i3]Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham:
A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB. CoRR abs/1806.06902 (2018) - 2017
- [j16]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
A Low-Latency Parallel Pipeline CORDIC. IEICE Trans. Electron. 100-C(4): 391-398 (2017) - [j15]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1102-1106 (2017) - [c33]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Katsumi Inoue, Osamu Shimojo, Cong-Kha Pham:
Highly parallel bitmap-based regular expression matching for text analytics. ISCAS 2017: 1-4 - [c32]Yuichiro Mori, Xuan-Thuan Nguyen, Cong-Kha Pham:
Reliable and energy-efficient transmission on the Internet-of-Video-Things. ISCIT 2017: 1-4 - [c31]Van-Phuc Hoang, Van-Tinh Nguyen, Anh-Thai Nguyen, Cong-Kha Pham:
A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process. MWSCAS 2017: 112-115 - [c30]Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, Nhu-Quynh Truong, Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham:
FPGA-based frequent items counting using matrix of equality comparators. MWSCAS 2017: 285-288 - [i2]Xuan-Thuan Nguyen, Trong-Tu Bui, Huu-Thuan Huynh, Duc-Hung Le, Cong-Kha Pham:
A Flexible High-Bandwidth Low-Latency Multi-Port Memory Controller. CoRR abs/1712.03477 (2017) - [i1]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion. CoRR abs/1712.03478 (2017) - 2016
- [j14]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
An FPGA approach for fast bitmap indexing. IEICE Electron. Express 13(4): 20160006 (2016) - [j13]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
An FPGA approach for high-performance multi-match priority encoder. IEICE Electron. Express 13(13): 20160447 (2016) - [c29]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process. ICICDT 2016: 1-4 - [c28]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Osamu Shimojo, Toshio Murayama, Kenji Tominaga, Cong-Kha Pham:
An efficient FPGA-based database processor for fast database analytics. ISCAS 2016: 1758-1761 - [c27]Trong-Thuc Hoang, Duc-Hung Le, Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
A hybrid adaptive CORDIC in 65nm SOTB CMOS process. ISCAS 2016: 2158-2161 - [c26]Van-Phuc Hoang, Van-Lan Dao, Cong-Kha Pham:
An ultra-low power AES encryption core in 65nm SOTB CMOS process. ISOCC 2016: 89-90 - [c25]Van-Phuc Hoang, Thi-Thanh-Dung Phan, Van-Lan Dao, Cong-Kha Pham:
A compact, ultra-low power AES-CCM IP core for wireless body area networks. VLSI-SoC 2016: 1-4 - 2015
- [j12]Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
Low-resource low-latency hybrid adaptive CORDIC with floating-point precision. IEICE Electron. Express 12(9): 20150258 (2015) - [j11]Trong-Thuc Hoang, Hong-Kiet Su, Hieu-Binh Nguyen, Duc-Hung Le, Huu-Thuan Huynh, Trong-Tu Bui, Cong-Kha Pham:
Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese. IEICE Electron. Express 12(14): 20150448 (2015) - [j10]Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [c24]Xuan-Thuan Nguyen, Cong-Kha Pham:
An efficient multi-port memory controller for multimedia applications. ASP-DAC 2015: 12-13 - [c23]Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham:
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. ICICDT 2015: 1-4 - [c22]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
SAR: A Self-Adaptive and Reliable protocol for wireless multimedia sensor networks. ICUFN 2015: 760-765 - [c21]Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
Parallel pipelining configurable multi-port memory controller for multimedia applications. ISCAS 2015: 2908-2911 - 2014
- [j9]Duc-Hung Le, Tran Bao Thuong Cao, Katsumi Inoue, Cong-Kha Pham:
A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA. IEICE Trans. Electron. 97-C(1): 65-76 (2014) - [c20]Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c19]Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - 2013
- [j8]Van-Phuc Hoang, Cong-Kha Pham:
Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 584-590 (2013) - [j7]Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham:
Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(9): 1883-1888 (2013) - [c18]Duc-Hung Le, Tran Bao Thuong Cao, Katsumi Inoue, Cong-Kha Pham:
A fast CAM-based Watermarking extraction on FPGA. ICICDT 2013: 207-210 - [c17]Duc-Hung Le, Tran Bao Thuong Cao, Katsumi Inoue, Cong-Kha Pham:
A fast CAM-based image matching system on FPGA. ISCAS 2013: 1797-1800 - [c16]Duc-Hung Le, Tran Bao Thuong Cao, Katsumi Inoue, Cong-Kha Pham:
A CAM-based Information Detection Hardware System for fast exact pattern matching. MWSCAS 2013: 848-851 - 2012
- [j6]Van-Phuc Hoang, Cong-Kha Pham:
Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(6): 999-1006 (2012) - [j5]Van-Phuc Hoang, Cong-Kha Pham:
An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(7): 1180-1184 (2012) - [j4]Duc-Hung Le, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham:
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(10): 1708-1717 (2012) - 2011
- [j3]Van-Phuc Hoang, Cong-Kha Pham:
An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(3): 995-998 (2011) - 2010
- [j2]Socheat Heng, Cong-Kha Pham:
A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 245-249 (2010) - [c15]Kimio Shibata, Cong-Kha Pham:
A DC-DC Converter using a high speed soft-start control circuit. ISCAS 2010: 833-836 - [c14]Kimio Shibata, Cong-Kha Pham:
A compact adaptive slope compensation circuit for Current-Mode DC-DC converter. ISCAS 2010: 1651-1654
2000 – 2009
- 2009
- [j1]Socheat Heng, Cong-Kha Pham:
A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator. IEICE Trans. Electron. 92-C(9): 1208-1214 (2009) - [c13]Socheat Heng, Weichun Tung, Cong-Kha Pham:
Low Power LDO with Fast Load Transient Response based on Quick Response Circuit. ISCAS 2009: 2529-2532 - 2007
- [c12]Cong-Kha Pham:
CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit. ACIS-ICIS 2007: 48-53 - [c11]Cong-Kha Pham, Koutaro Yamano:
An Edge Extraction Method for Color Image Using Multiple-Valued LoG Filter and Color Space. ACIS-ICIS 2007: 658-662 - [c10]Socheat Heng, Cong-Kha Pham:
Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance. ECCTD 2007: 120-123 - 2006
- [c9]Cong-Kha Pham, Wataru Noguchi:
A hardware accelerator for solving the n-queen problem. Computational Intelligence 2006: 150-155 - [c8]Cong-Kha Pham:
Simple Logic Threshold Conversion Circuits. ICECS 2006: 268-271 - [c7]Wataru Noguchi, Cong-Kha Pham:
A Proposal to Solve N-Queens Problems Using Maximum Neuron Model with A Modified Hill-Climbing Term. IJCNN 2006: 2679-2682 - 2005
- [c6]Cong-Kha Pham, Hiroshi Yamashita:
Tolerance on Geometrical Operation as an Attack to Watermarked JPEG Image. KES (1) 2005: 1199-1204 - 2001
- [c5]Cong-Kha Pham:
A novel synapses circuit and its application to a neural-based A/D converter. ISCAS (3) 2001: 612-615
1990 – 1999
- 1995
- [c4]Cong-Kha Pham, Tetsuya Kimura, Munemitsu Ikegami, Mamoru Tanaka:
Pulse coded cellular neural network and it's hardware implementation. ICNN 1995: 1590-1594 - [c3]Mitsuhisa Kanaya, Masako Takahira, Toshirou Watanabe, Cong-Kha Pham, Mamoru Tanaka:
Associative Dynamics of Competitive Cellular Neural Network. ISCAS 1995: 1152-1155 - 1994
- [c2]Cong-Kha Pham, Mamoru Tanaka, Katsufusa Shono:
Bifurcation and Chaos in CMOS Inverters Ring Oscillator. ISCAS 1994: 697-700 - 1993
- [c1]Cong-Kha Pham, Munemitsu Ikegami, Mamoru Tanaka, Katsufusa Shono:
CMOS digital retina chip with multi-bit neurons for image coding. ISCAS 1993: 2752-2755
Coauthor Index
[j62] [j61] [j60] [j59] [j58] [j57] [j56] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [j55] [j54] [j53] [j52] [j51] [j47] [c62] [c61] [c60] [c59] [j45] [j44] [j42] [j41] [j40] [j39] [c57] [c56] [c55] [c54] [c53] [c52] [j38] [j37] [j36] [j35] [j34] [j33] [j31] [c51] [c50] [c49] [c48] [j30] [j29] [j27] [c46] [j26] [j25] [j24] [j23] [c43] [c42] [c41] [j22] [j21] [j20] [j19] [c37] [c36] [c35] [c34] [i5] [i4] [i3] [c30] [c28] [c27] [j12] [j11]
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