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ORCIDVLSI-DAT 2018: Hsinchu, Taiwan
- 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018. IEEE 2018, ISBN 978-1-5386-4260-3
- Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue
, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka:
A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. 1-4 - Siang-Wei Wang, Tse-An Chen, Kuan-Hung Chen, Chia-Ling Wei:
Design of divider circuit for electrochemical impedance spectroscopy measurement system. 1-4 - Xiaohua Huang, Han Liu, Woogeun Rhee, Zhihua Wang:
A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems. 1-4 - Sheng-Lyang Jang, Ke Jen Lin, Wen-Cheng Lai, Miin-Horng Juang:
A capacitive cross-coupled GaN HEMT injection-locked frequency divider. 1-3 - Sheng-Di Lin:
CMOS single-photon detectors for vehicle LiDAR - status and trends. 1 - Lei Gao:
Safe and secure SOC architecture for autonomous driving. 1 - Darren Chen:
V2V & V2I for connected vehicle. 1 - Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang:
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. 1-4 - Fu-Lian Wong, Li-Cheng Zheng, Yung-Chih Chen:
Optimization of threshold logic networks with ODC-based node merging. 1-4 - Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
An Ising model mapping to solve rectangle packing problem. 1-4 - Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho:
SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. 1-4 - Tian-Sheuan Chang:
End-to-end hardware accelerator for deep convolutional neural network. 1 - Simon See:
Efficient method for AI computing. 1 - Chung-Ho Chen:
A glance of the CASLab HSAIL SIMT GPU for OpenCL and TensorFlow applications. 1 - Harry H. Chen:
Beyond structural test, the rising need for system-level test. 1-4 - Subagaran Letchumanan, Terrence Huat Hin Tan, Yee Pheng Gan, Sai Leong Wong:
Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM). 1-3 - Eugene Yang:
Fuzz testing & software composition analysis in software engineering. 1-3 - Hung-Yi Hsieh, Pin-Yi Li, Cheng-Han Yang, Kea-Tiong Tang:
A high learning capability probabilistic spiking neural network chip. 1-4 - Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee:
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. 1-4 - Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu:
MORAS: An energy-scalable system using adaptive voltage scaling. 1-4 - Yen-Lin Lee, Pei-Kuei Tsung, Max Wu:
Techology trend of edge AI. 1-2 - Pei-Jung Liang, Peter Chondro, Jheng-Rong Wu, Wei-Hao Lai, Yi-Fa Sun, Yi-Chen Lai, Tse-Min Chen:
Deep fusion of heterogeneous sensor modalities for the advancements of ADAS to autonomous vehicles. 1-4 - Chang-Jiun Chen, Kai-Chun Chen, May-chen Martin-Kuo:
Acceleration of neural network model execution on embedded systems. 1-3 - Yutaka Adachi, Chihiro Matsui, Ken Takeuchi:
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. 1-4 - Kun-Chih Jimmy Chen, Po-Chen Chien:
A fast ECG diagnosis by using spectral artificial neural network (SANN) approach. 1-4 - Yi-Chin Tsai, Kuan-Hung Chen, Yun Chen, Jih-Hsiang Cheng:
Accurate and fast obstacle detection method for automotive applications based on stereo vision. 1-4 - Kun-Ying Yeh, Yu-Jie Huang, Tung-Chien Chen, Liang-Gee Chen, Shey-Shi Lu:
A 473 μW wireless 16-channel neural recording SoC with RF energy harvester. 1-4 - Kun-Ying Yeh, Ting-Hao Lin, Yi-Yen Hsieh, Chia-Ming Chang, Yao-Joe Yang, Shey-Shi Lu:
A cuffless wearable system for real-time cutaneous pressure monitoring with cloud computing assistance. 1-4 - Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, Hao-Sheng Wu:
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process. 1-4 - Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara:
High-throughput Von Neumann post-processing for random number generator. 1-4 - Jheng-Hao Ye, Ming-Der Shieh:
High-performance NTT architecture for large integer multiplication. 1-4 - Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang:
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. 1-4 - Sashi Obilisetty:
Digital intelligence and chip design. 1-4 - Weibin Ding:
Machine learning further improving place and route QoR. 1 - Bauli Yan:
Machine learning opportunities and applications in SoC design. 1 - You-Te Chiu, Yu-Hsuan Liu, Chung-Chih Hung:
A high-performance current-mode DC-DC buck converter with adaptive clock control technique. 1-4 - Chun-Ping Niou, Chien-Hung Tsai, Ta-Jin Chen:
A digital peak current delay compensation for primary-side regulation flyback adapter. 1-4 - Fangyu Mao, Yan Lu, Seng-Pan U, Rui Paulo Martins:
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. 1-4 - Yu-Yi Wu, Shih-Hsu Huang:
TSV-aware 3D test wrapper chain optimization. 1-4 - Takahiro Nakayama, Masanori Hashimoto:
Hold violation analysis for functional test of ultra-low temperature circuits at room temperature. 1-4 - Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li:
Parallel order ATPG for test compaction. 1-4 - Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee:
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. 1-4 - Shen-Fu Hsiao, Chih-Hsuan Chang:
Hardware design of disparity computation for stereo vision using guided image filtering. 1-4 - Kaship Sheikh, Lan Wei:
Using approximate circuits to counter process imperfections in CNFET based circuits. 1-4 - Feng Zhang, Dongyu Fan, Qi-Peng Lin, Qiang Huo, Yun Li, Lan Dai, Cheng-Ying Chen, Haihua Shen:
The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory. 1-4 - Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
On IC traceability via blockchain. 1-4 - Naofumi Homma:
Side-channel-aware LSI design. 1 - Shih-Lien Lu:
A foundry's view of hardware security. 1 - Li-Chin Chen, Chien-Chia Huang, Yao-Lin Chang, Hung-Ming Chen:
A learning-based methodology for routability prediction in placement. 1-4 - Hua-Yi Wu, Shao-Yun Fang:
Triple patterning lithography-aware detailed routing ensuring via layer decomposability. 1-4 - Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, James Chien-Mo Li:
Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations. 1-4 - Yan-Shiun Wu, Hong-Yan Su, Yi-Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li:
MapReduce-based pattern classification for design space analysis. 1-4 - Kevin Zhang:
Circuit design in nano-scale CMOS technologies. 1 - Jan M. Rabaey:
Homo technologicus. 1 - Christian Fager, Mattias Thorsell, Emanuel Baptista, Koen Buisman, Johan Bremer, Johan Bergsten, Niklas Rorsman:
Analysis of thermal effects in integrated radio transmitters. 1-2 - Stanley Seungchul Song:
Unified technology optimization platform using integrated analysis (UTOPIA) for holistic pathfinding DTCO of advanced transistors. 1 - John R. Hu, James Chen, Boon-khim Liew, Yanfeng Wang, Lianxi Shen, Lin Cong:
Systematic co-optimization from chip design, process technology to systems for GPU AI chip. 1-2 - David Z. Pan:
Machine learning for IC design and technology co-optimization in extreme scaling. 1 - Subhasish Mitra:
Abundant-data computing: The N3XT 1, 000X. 1 - David M. Brooks:
Co-designed systems for deep learning hardware accelerators. 1 - Chia-Hong Jan:
Moore's law - predict the unpredictable. 1 - Hoi-Jun Yoo:
Mobile/embedded DNN and AI SoCs. 1 - Xiaoxiong Gu, Bodhisatwa Sadhu, Duixian Liu, Christian W. Baks, Alberto Valdes-Garcia:
Antenna-in-package design and module integration for millimeter-wave communication and 5G. 1-2 - Sebastian Wolfgang Sattler, Fabrizio Gentili, Reinhard Teschl, Carlos Carceller, Wolfgang Bösch:
Emerging technologies and concepts for 5G applications - A. making additive manufactured ceramic microwave filters ready for 5G. 1-6 - Florian Huhn, Andreas Wentzel, Wolfgang Heinrich:
GaN-based digital transmitter architectures for 5G. 1-2 - Chih-Yuan Lin:
5G mmWave communication: From system concept to implementation. 1 - Chien-Nan Kuo:
Phased array technique for mm-wave wireless communication. 1 - Chia-Hsiang Yang:
Massive MIMO detection VLSI design. 1 - Frédéric Boeuf:
Silicon photonics : From research to industrial reality. 1 - Chieh-Chih Bob Wang:
Self-driving cars: Technologies, business opportunities and challenges. 1
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