Keynote

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  Robert A. Iannucci: Platform Thinking in Embedded Systems. 1

Reconfigurable System Design and Implementations

• 
  Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis: Interprocedural Optimization for Dynamic Hardware Configurations. 2-11
• 
  Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf: Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. 12-21
• 
  Humberto Calderon, Stamatis Vassiliadis: Reconfigurable Multiple Operation Array. 22-31
• 
  Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch: RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. 32-40
• 
  Ricardo S. Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto: Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. 41-50
• 
  Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. 51-61
• 
  Pablo Robelly, Arne Lehmann, Gerhard Fettweis: Two-Dimensional Fast Cosine Transform for Vector-STA Architectures. 62-71
• 
  Guy Gogniat, Wayne Burleson, Lilian Bossuet: Configurable Computing for High-Security/High-Performance Ambient Systems. 72-81
• 
  Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos: FPL-3E: Towards Language Support for Reconfigurable Packet Processing. 82-92

Processor Architectures, Design and Simulation

• 
  Georgi Gaydadjiev, Stamatis Vassiliadis: Flux Caches: What Are They and Are They Useful? 93-102
• 
  Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon: First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. 103-111
• 
  Yiyu Tan, Chihang Yau, Kaiman Lo, Pak Lun Mok, Anthony S. Fong: A Novel JAVA Processor for Embedded Devices. 112-121
• 
  Tomi Westerlund, Juha Plosila: Formal Specification of a Protocol Processor. 122-131
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  Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho: Tuning a Protocol Processor Architecture Towards DSP Operations. 132-141
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  Olli Silvén, Kari Jyrkkä: Observations on Power-Efficiency Trends in Mobile Communication Devices. 142-151
• 
  Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane: CORDIC-Augmented Sandbridge Processor for Channel Equalization. 152-161
• 
  Sung-Hoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon: Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic. 162-171
• 
  Fei Gao, Suleyman Sair: Exploiting Intra-function Correlation with the Global History Stack. 172-181
• 
  Dinesh C. Suresh, Walid A. Najjar, Jun Yang: Power Efficient Instruction Caches for Embedded Systems. 182-191
• 
  Lucanus J. Simonson, Lei He: Micro-architecture Performance Estimation by Formula. 192-201
• 
  Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere: Offline Phase Analysis and Optimization for Multi-configuration Processors. 202-211
• 
  Teemu Pitkänen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala: Hardware Cost Estimation for Application-Specific Processor Design. 212-221
• 
  Stefan Farfeleder, Andreas Krall, R. Nigel Horspool: Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures. 222-231
• 
  Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen: Generating Stream Based Code from Plain C. 232-241
• 
  Sangchul Han, Moonju Park, Yookun Cho: Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First. 242-250
• 
  Dan Zhang, Zeng-zhi Li, Hong Song, Long Liu: A Programming Model for an Embedded Media Processing Architecture. 251-261
• 
  Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos: Automatic ADL-Based Assembler Generation for ASIP Programming Support. 262-268
• 
  C. John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael J. Schulte, Stamatis Vassiliadis: Sandbridge Software Tools. 269-278

Architectures and Implementations

• 
  Philippe Marchand, Purnendu Sinha: A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems. 279-288
• 
  Sunil Kim: Pattern Matching Acceleration for Network Intrusion Detection Systems. 289-298
• 
  SungHwan Lee, JongSu Yi, JunSeong Kim: Real-Time Stereo Vision on a Reconfigurable System. 299-307
• 
  Ali Manzak, Hüseyin Göksu: Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design. 308-313
• 
  Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung: Compressed Swapping for NAND Flash Memory Based Embedded Systems. 314-323
• 
  David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen: A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms. 324-333
• 
  Chunhui Zhang, Yun Long, Fadi J. Kurdahi: A Scalable Embedded JPEG2000 Architecture. 334-343
• 
  Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan: A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. 344-353
• 
  Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen: Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. 354-363
• 
  Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso: DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor. 364-373

System Level Design, Modeling and Simulation

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  Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll: Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. 374-383
• 
  Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen: High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks. 384-393
• 
  Maziar Goudarzi, Shaahin Hessabi: The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models. 394-403
• 
  Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen: Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow. 404-413
• 
  John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson: Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. 414-423
• 
  Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz: DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. 424-433
• 
  Sören Sonntag, Matthias Gries, Christian Sauer: SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. 434-444
• 
  Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene: Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications. 445-454
• 
  Andy D. Pimentel: A Case for Visualization-Integrated System-Level Design Space Exploration. 455-464
• 
  Stefan Eilers, Christian Müller-Schloer: s Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of Concept. 465-474

last updated on Tue May 21 02:26:57 2013 by the dblp team
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