MPSOC

• 
  Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka: Overview of the Scalable Communications Core. 3-8
• 
  Youssef Atat, Nacer-Eddine Zergainoh: Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. 9-14
• 
  Magnus Själander, Per Larsson-Edefors, Magnus Björk: A Flexible Datapath Interconnect for Embedded Applications. 15-20
• 
  Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert: HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems. 21-28

Reconfigurable Systems

• 
  Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Technological hybridization for efficient runtime reconfigurable FPGAs. 29-34
• 
  Alisson Vasconcelos De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher: Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. 35-40
• 
  Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. 41-46
• 
  Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro: Transparent Dataflow Execution for Embedded Applications. 47-54

Methods for Optimized Placement

• 
  Kostas Siozios, Dimitrios Soudris: A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. 55-60
• 
  Ricardo S. Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso: A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures. 61-66
• 
  Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis: 3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. 67-72
• 
  Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Minimum-Congestion Placement for Y-interconnects: Some studies and observations. 73-80

VLSI System Design, Methods and Tools

• 
  Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfgang H. Krautschneider: Design of a MCML Gate Library Applying Multiobjective Optimization. 81-85
• 
  Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth: Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. 86-91
• 
  Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto: A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. 92-97
• 
  Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin: Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications. 98-106

Methods for Low Power Design I

• 
  Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. 107-112
• 
  Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai: Design and Analysis of Low Power Dynamic Bus Based on RLC simulation. 113-118
• 
  Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong: Interconnect Power Optimization Based on Timing Analysis. 119-124
• 
  Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson: Overdrive Power-Gating Techniques for Total Power Minimization. 125-132

Mixed Signal Design

• 
  Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf: Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results. 133-138
• 
  Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers. 139-144
• 
  Angan Das, Ranga Vemuri: An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. 145-152

Verification and Test Methodology I

• 
  Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak: Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. 153-158
• 
  Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Coverage Driven Verification applied to Embedded Software. 159-164
• 
  Ulrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. 165-170
• 
  Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. 171-178

Verification and Test Methodology II

• 
  Teng Lin, Jianhua Feng, Yangyuan Wang: A New Test Data Compression Scheme for Multi-scan Designs. 179-185
• 
  João M. S. Silva, L. Miguel Silveira: On the Compressibility of Power Grid Models. 186-191
• 
  Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell: Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. 192-197
• 
  Alair Dias Jr., Diógenes Cecilio da Silva Jr.: Code-coverage Based Test Vector Generation for SystemC Designs. 198-206

Physical Design I

• 
  Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. 207-212
• 
  Taraneh Taghavi, Majid Sarrafzadeh: Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks. 213-218
• 
  Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi: An Efficient Analytical Approach to Path-Based Buffer Insertion. 219-224
• 
  Narender Hanchate, Nagarajan Ranganathan: Integrated Gate and Wire Sizing at Post Layout Level. 225-232

Physical Design II

• 
  Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira: Generating Realistic Stimuli for Accurate Power Grid Analysis. 233-238
• 
  Hailong Yao, Yici Cai, Xianlong Hong: CMP-aware Maze Routing Algorithm for Yield Enhancement. 239-244
• 
  Narender Hanchate, Nagarajan Ranganathan: Statistical Gate Sizing for Yield Enhancement at Post Layout Level. 245-252

SoC Embedded Processing

• 
  Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado: Automatic Retargeting of Binary Utilities for Embedded Code Generation. 253-258
• 
  Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf: A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. 259-264
• 
  Frederico De Faria, Marius Strum, Wang Jiang Chau: A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. 265-272

VLSI Circuits

• 
  Saihua Lin, Huazhong Yang, Rong Luo: High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit. 273-278
• 
  Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai: Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. 279-284
• 
  J. Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot: Design of a Novel CNTFET-based Reconfigurable Logic Gate. 285-290
• 
  Shubhankar Basu, Ranga Vemuri: Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. 291-298

NoC

• 
  José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis: Inserting Data Encoding Techniques into NoC-Based Systems. 299-304
• 
  Brett Feero, Partha Pratim Pande: Performance Evaluation for Three-Dimensional Networks-On-Chip. 305-310
• 
  Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris: Application - specific NoC platform design based on System Level Optimization. 311-316
• 
  Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu: Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding. 317-324

IP and Design, VLSI System Design

• 
  Di Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn: Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. 325-330
• 
  Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto: A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. 331-336
• 
  James E. Stine, Jeff M. Blank: Partial Product Reduction for Parallel Cubing. 337-342
• 
  Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. 343-350

System Level Design

• 
  Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo: A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. 351-356
• 
  Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz: Designing Memory Subsystems Resilient to Process Variations. 357-363
• 
  Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras: Asymmetrically Banked Value-Aware Register Files. 363-368
• 
  Andrew Tam, Sazzadur Chowdhury: A MEMS Ultra-Stable Short Duration Current Pulse Generator. 369-374
• 
  Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin: Investigating Simple Low Latency Reliable Multiported Register Files. 375-382

Methods for Low Power Design II

• 
  Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. 383-388
• 
  Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay: A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs. 389-394
• 
  Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos: On the Limitations of Power Macromodeling Techniques. 395-400
• 
  K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas: Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. 401-408

Emerging Trends in VLSI

• 
  Hyunjin Lee, Sangyeun Cho, Bruce R. Childers: Performance of Graceful Degradation for Cache Faults. 409-415
• 
  Marinos Sampson, Dimitrios Voudouris, George K. Papakonstantinou: A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions. 416-421
• 
  Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram: Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets. 422-427
• 
  Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. 428-436

Poster Session I

• 
  Abdel Ejnioui: FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. 437-438
• 
  Jer-Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun: A Novel Reconfigurable Computation Unit for DSP Applications. 439-444
• 
  Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi: Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. 445-446
• 
  Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu: Vector Processing Support for FPGA-Oriented High Performance Applications. 447-448
• 
  Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto: An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. 449-450
• 
  Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes: MOTIM - A Scalable Architecture for Ethernet Switches. 451-452
• 
  Avishek Saha, Santosh Ghosh, Shamik Sural, Jayanta Mukherjee: Toward Memory-efficient Design of Video Encoders for Multimedia Applications. 453-454
• 
  Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko: MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems. 455-456
• 
  Simone Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto: Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. 457-458
• 
  Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. 459-460
• 
  Fabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra dos Santos: High Level RTOS Scheduler Modeling for a Fast Design Validation. 461-466
• 
  Luciano Severino de Paula, Eric E. Fabris, Sergio Bampi, Altamiro Amadeu Susin: A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator. 467-470

Poster Session II

• 
  Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram: A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation. 471-472
• 
  Charles Thangaraj, Tom Chen: Power andPerformance Analysis for Early Design Space Exploration. 473-478
• 
  Fekri Kharbash, Ghulam M. Chaudhry: Reliable Binary Signed Digit Number Adder Design. 479-484
• 
  Hector Kirschenbaum, Alejandro De la Plaza: Voltage Pump Based on Self Clocked Cells. 485-487
• 
  Mohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami: Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks. 488-489
• 
  Vahid Moalemi, Ali Afzali-Kusha: Subthreshold Pass Transistor Logic for Ultra-Low Power Operation. 490-491
• 
  Zhaolin Li, Gongqiong Li: Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence. 492-497
• 
  Franco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julián, Pablo Sergio Mandolesi: A comparison of low power architectures for digital delay measurement. 498-499
• 
  Salvador Ortiz, Roberto Suaya: Efficient implementation of conduction modes for modelling skin effect. 500-505
• 
  M. Khalilzadeh, A. Nabavi: A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications. 506-507
• 
  Nainesh Agarwal, Nikitas J. Dimopoulos: DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. 508-509
• 
  Yokesh Kumar, Prosenjit Gupta: An External Memory Circuit Validation Algorithm for Large VLSI Layouts. 510-511
• 
  Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling Subthreshold Leakage Current in General Transistor Networks. 512-513
• 
  Vahid Moalemi, Ali Afzali-Kusha: Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies. 514-515
• 
  Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud: Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. 516-517

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