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  2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA. IEEE Computer Society 2001 ISBN 0-7695-1025-6

Tutorial

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  Yervant Zorian: System-on-Chip: Embedded Test Strategies. 7
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  Kaushik Roy, Ali Keshavarzi: Design and Test of Low Voltage CMOS Circuits. 7
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  Mo Tamjidi, Bejoy G. Oomman: Redundancy Requirements for Embedded Memories. 8
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  Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats: Design Metrics to Achieve Design Quality. 9
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  Phil Dworsky, Warren Savage: Fundamental Methods to Enable SoC Design and Reuse. 9
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  Charvaka Duvvury: Issues in Deep Submicron State-of-the-Art ESD Design. 10
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  Noel R. Strader, Gérard Memmi, Carl Pixley: Application of Formal Verification to Design Creation and Implementation. 11
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  Magdy S. Abadir, Li-C. Wang: Verification and Validation of Complex Digital Systems: An Industrial Perspective. 11-12
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  Daniel Foty, David Binkley: Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality. 13
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  Narain Arora, N. S. Nagaraj: Interconnect Modeling for Timing, Signal Integrity and Reliability. 13
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  David Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. 14

Evening Panel Discussion

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  Rick Merritt, Richard Goering: The 50-Million Transistor Chip: The Quality Challenge for 2001. 15-

Plenary Session

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  Tak Young: Monterey Design. 19-20
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  Hajimi Sasaki: Future Platform for Mobile Communication. 21-22
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  Joe Costello: Delivering Quality Delivers Profits. 23-24
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  Raul Camposano: The Expanding Use of Formal Techniques in Electronic Design. 25-26
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  Edward C. Ross: IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design. 27-

Impact of Verification on Complex SOC Quality

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  Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman: Stopping Criteria Comparison: Towards High Quality Behavioral Verification. 31-37
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  Umberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto: Concrete Impact of Formal Verification on Quality in IP Design and Implementation. 38-43
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  Zan Yang, Byeong Min, Gwan Choi: Simulation Using Code-Perturbation: Black- and White-Box Approach. 44-49
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  F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi: A "Design for Verification" Methodology. 50-55
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  Mohammed El Shobaki, Lennart Lindh: A Hardware and Software Monitor for High-Level System-on-Chip Verification. 56-

Quality of EDA Tools and Design Methodologies

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  Paul Kartschoke, Shervin Hojat: Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. 65-70
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  Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous: I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. 71-75
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  Giora Ben-Yaacov, Edward P. Stone, Richard Goldman: Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software. 76-80
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  Andrew B. Kahng, Stefanus Mantik: A System for Automatic Recording and Prediction of Design Quality Metrics. 81-86
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  Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick: Scripting for EDA Tools: A Case Study. 87-

Design, Fabrication and Reliability Challenges for Emerging Technologies

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  Akira Matsuzawa: High Quality Analog CMOS and Mixed Signal LSI Design. 97-104
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  Kenneth L. Shepard: CAD Issues for CMOS VLSI Design in SOI. 105-110
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  Sheldon Wu, Fred Wang, Lie-Szu Juang: Foundry's Perspective of System Integration: Quality Design and Time-to-Volume. 111-116
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  Choshu Ito, Kaustav Banerjee, Robert W. Dutton: Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. 117-122
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  J. W. McPherson: Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts. 123-

Capacitive Crosstalk Analysis

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  Ninglong Lu, Ibrahim N. Hajj: A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. 133-138
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  Pirouz Bazargan-Sabet, Fabrice Ilponse: A Model for Crosstalk Noise Evaluation in Deep Submicron Processes. 139-144
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  Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani: Noise Model for Multiple Segmented Coupled RC Interconnects. 145-150
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  Qingjian Yu, Ernest S. Kuh: New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. 151-157
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  Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. 158-

Interconnect Modeling and Analysis

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  Asim Husain: Models For Interconnect Capacitance Extraction. 167-172
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  Tom Chen: Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. 173-178
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  Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada: Computational Cost Reduction in Extracting Inductance. 179-184
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  Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie: Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. 185-190
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  Mehdi M. Mechaik: Signal Attenuation in Transmission Lines. 191-

Power-Aware Design

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  Wei-Chung Cheng, Massoud Pedram: Memory Bus Encoding for Low Power: A Tutorial. 199-204
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  Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj: RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 205-210
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  Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa: Instruction Prediction for Step Power Reduction. 211-216
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  Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. 217-222
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  Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez: A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits. 223-

Evening Panel Discussion

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  Bill Alexander, Jacques Benkoski: 0.13 micron: Will the Speed Bumps Slow the Race to Market? 229-

Plenary Session II

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  Wojciech Maly: Quality of Design from an IC Manufacturing Perspective. 235-236
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  Vinod Agrawal: Embedded Test Leads to Embedded Quality. 237-238
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  Aki Fujimura: Quality on Time. 239-240
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  Philippe Magarshack: Quality of SoC Designs through Quality of the Design Flow: Status and Needs. 241-

Ph.D. Student Forum

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  Nguyen Quang Trung, Krystyna Siekierska: Soft Core Based Model of a Microcomputer Family. 245-246
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  Tung-Yang Chen, Ming-Dou Ker: Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. 247-248
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  Subhasish Mitra, Edward J. McCluskey: Diversity Techniques for Concurrent Error Detection. 249-250
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  Peter Verplaetse: Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling. 251-252
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  Vlado Vorisek: Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level. 253-254
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  S. Klupsch: Design, Integration and Validation of Heterogeneous Systems. 255-256
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  Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj: RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 257-

Poster Session

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  Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang: Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. 267-272
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  Alexander Zemliak: One Approach to Analog System Design Problem Formulation. 273-278
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  Mark Birnbaum, Charlene C. Johnson: VSIA Quality Metrics for IP and SoC. 279-283
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  Wei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates: Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology. 284-289
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  Tom Egan, Samiha Mourad: Verification of Embedded Phase-Locked Loops. 290-295
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  Alexander Korshak, Jyh-Chwen Lee: An Effective Current Source Cell Model for VDSM Delay Calculation. 296-300
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  Mehdi M. Mechaik: An Evaluation of Single-Ended and Differential Impedance in PCBs. 301-306
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  Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng: HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. 307-312
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  Ning Zhu, Han Young Koh: Power Grid Modeling Technique for Hierarchical Power Network Analysis. 313-318
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  Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy Efficient Signaling in Deep Submicron CMOS Technology. 319-324
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  Rong Lin: Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. 325-330
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  Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca: Complex Reliability Evaluation of Voters for Fault Tolerant Designs. 331-336
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  Josef Schmid, Timo Schüring, Christoph Smalla: Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. 337-342
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  Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. 343-349
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  Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos: On Accumulator-Based Bit-Serial Test Response Compaction Schemes. 350-

Defect Analysis and Test Generation

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  Michel Renovell: Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. 359-364
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  Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. 365-371
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  Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou: Automatic Functional Vector Generation Using the Interacting FSM Model. 372-377
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  Jayant Deodhar, Spyros Tragoudas: Color Counting and its Application to Path Delay Fault Coverage. 378-383
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  Maria K. Michael, Spyros Tragoudas: ATPG for Path Delay Faults without Path Enumeration. 384-

Design of Programmable and Platform-Based IP

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  Rafael Peset Llopis, Marcel Oosterhuis, Ramanathan Sethuraman, Paul E. R. Lippens, Albert van der Werf, Steffen Maul, Jim Lin: HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec. 393-398
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  Martin Speitel, Michael Schlicht, Martin Leyh: Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis. 399-404
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  Chih-Yuan Chen, Shing-Wu Tung: ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. 405-408
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  Artur Chojnacki, Lech Józwiak: High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. 409-414
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  Kazimierz Wiatr, Ernest Jamro: Implementation of Multipliers in FPGA Structures. 415-

Embedded Panel Discussion

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  Nader Vasseghi, Steve Ohr: Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life? 421-

Design for Manufacturability

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  Ron Ross, Keith McCasland: Early Detection of Design Sensitivities that Cause Yield Loss for New Products. 427-430
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  Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu: Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. 431-436
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  Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long: Timing Yield Estimation from Static Timing Analysis. 437-442
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  Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong: Performance Improvement for High Speed Devices Using E-tests and the SPICE Model. 443-

Embedded Memories

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  Pierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma: A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. 451-455
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  Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas: Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. 456-461
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  Nai-Yin Sung, Tsung-Yi Wu: A Method of Embedded Memory Access Time Measurement. 462-

Device Modeling and Design Quality

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  Amit Mehrotra: Noise in Radio Frequency Circuits: Analysis and Design Implications. 469-476
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  Peter Bendix: Spice Model Quality: Process Development Viewpoint. 477-481
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  Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. 482-487
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  Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli: Modeling of Substrate Noise Injected by Digital Libraries. 488-