Keynote Speeches

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  Shaojun Wei: Reconfigurable computing - evolution of Von Neumann architecture.
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  Ivo Bolsens: FPGA platforms leading the way in the application of 'more than Moore's' technology.
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  James Truchard: Bringing FPGA design to application domain experts.
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  Stephen Brown: Technology issues facing the world's largest integrated circuits.
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  Albert Wang: In search for better silicon and human efficiency.

Architectures

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  Assem A. M. Bsoul, Steven J. E. Wilton: An FPGA architecture supporting dynamically controlled power gating. 1-8
• 
  Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: A tiled programmable fabric using QCA. 9-16
• 
  Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi, Fabien Clermidy, Luca Perniola, Ian O'Connor: Phase-change-memory-based storage elements for configurable logic. 17-20
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  Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga: Dynamic reconfigurable bit-parallel architecture for large-scale regular expression matching. 21-28

Parallel Implementation and CAD

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  Shanyuan Gao, Andrew G. Schmidt, Ron Sass: Impact of reconfigurable hardware on accelerating MPI_Reduce. 29-36
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  Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton: Accelerating HMMER on FPGA using parallel prefixes and reductions. 37-44
• 
  Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris: Multiple data set reduction on FPGAs. 45-52
• 
  Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tony Frangieh, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson: Accelerating FPGA development through the automatic parallel application of standard implementation tools. 53-60
• 
  Steven Birk, J. Gregory Steffan, Jason Helge Anderson: Parallelizing FPGA placement using Transactional Memory. 61-69

Multi-Core and Multi-FPGA

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  Qingbo Wang, Weirong Jiang, Yinglong Xia, Viktor K. Prasanna: A message-passing multi-softcore architecture on FPGA for Breadth-first Search. 70-77
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  Marcel Gort, Jason Helge Anderson: Deterministic multi-core parallel routing for FPGAs. 78-86
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  Henning Manteuffel, Cem Savas Bassoy, Friedrich Mayer-Lindenberg: The TransC process model and interprocess communication. 87-93
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  Brahim Betkaoui, David B. Thomas, Wayne Luk: Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. 94-101
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  Luzhou Wang, Kentaro Sano, Satoru Yamamoto: Local-and-global stall mechanism for systolic computational-memory array on extensible multi-FPGA system. 102-109

Arithmetic

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  Florent de Dinechin, Bogdan Pasca: Floating-point exponential functions for DSP-enabled FPGAs. 110-117
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  Miaoqing Huang, David L. Andrews: Modular design of fully pipelined accumulators. 118-125
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  Álvaro Vázquez, Florent de Dinechin: Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. 126-133
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  Guiming Wu, Yong Dou, Miao Wang: High performance and memory efficient implementation of matrix multiplication on FPGAs. 134-137

Robust and Secure Computing

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  Haile Yu, Qiang Xu, Philip Heng Wai Leong: Fine-grained characterization of process variation in FPGAs. 138-145
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  Michael Kasper, Werner Schindler, Marc Stöttinger: A stochastic method for security evaluation of cryptographic FPGA implementations. 146-153
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  Stavros Tzilis, Ioannis Sourdis, Georgi Gaydadjiev: Fine-grain fault diagnosis for FPGA logic blocks. 154-161
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  Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A robust reconfigurable logic device based on less configuration memory logic cell. 162-169
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  Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki: Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. 170-177

Applications

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  Yingxi Lu, Keanhong Boey, Philip Hodgers, Máire O'Neill: Lightweight DPA resistant solution on FPGA to counteract power models. 178-183
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  Yuichiro Utan, Shin'ichi Wakabayashi, Shinobu Nagayama: An FPGA-based text search engine for approximate regular expression matching. 184-191
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  Jianyun Zhu, Tsutomu Maruyama: Real-time detection of line segments on FPGA. 192-199
• 
  Tim Güneysu: True random number generation in block memories of reconfigurable devices. 200-207

Routing and Scheduling

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  Dirk Koch, Christian Beckhoff, Jim Torresen: Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems. 208-215
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  Omesh Mutukuda, Andy Ye, Gul Khan: The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources. 216-223
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  Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua: ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks. 224-232
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  Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk: Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. 233-240

Special Session

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  Yaxuan Qi, Jeffrey Fong, Weirong Jiang, Bo Xu, Jun Li, Viktor K. Prasanna: Multi-dimensional packet classification on FPGA: 100 Gbps and beyond. 241-248
• 
  Guiming Wu, Yong Dou, Miao Wang: Automatic synthesis of processor arrays with local memories on FPGAs. 249-252
• 
  Zhengmeng Lei, Lunkai Zhang, Fenglong Song, Shibin Tang, Dongrui Fan: GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging. 253-256
• 
  Liangwei Ge, Zhenan Tang, Kaiyu Wang, Ming Cao, Wencong Zou, Dong Liu: Synthesis of a unified unit for evaluating an application-specific set of elementary functions. 257-260
• 
  Jing Yan, Ning-Yi Xu, Zenglin Xia, Rong Luo, Feng-Hsiung Hsu: A compression method for inverted index and its FPGA-based decompression solution. 261-264
• 
  Jian Ouyang, Hong Luo, Zilong Wang, Jiazi Tian, Chenghui Liu, Kehua Sheng: FPGA implementation of GZIP compression and decompression for IDC services. 265-268

Poster Session

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  Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson: Application-specific hardware accelerator for implementing recursive sorting algorithms. 269-272
• 
  Vinay Sriram, David Cox, Kuen Hung Tsoi, Wayne Luk: Towards an embedded biologically-inspired machine vision processor. 273-278
• 
  Nadim Nasreddine, Jean-Louis Boizard, Christophe Escriba, Jean-Yves Fourniols: Wireless sensors networks emulator implemented on a FPGA. 279-282
• 
  Markos Papadonikolakis, Christos-Savvas Bouganis: A novel FPGA-based SVM classifier. 283-286
• 
  Hoang Le, Viktor K. Prasanna: High-throughput IP-lookup supporting dynamic routing tables using FPGA. 287-290
• 
  André Seffrin, Sunil Malipatlolla, Sorin A. Huss: A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability. 291-294
• 
  Thomas Marconi, Dimitris Theodoropoulos, Koen Bertels, Georgi Gaydadjiev: A novel HDL coding style to reduce power consumption for reconfigurable devices. 295-299
• 
  Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano: Wire congestion aware synthesis for a dynamically reconfigurable processor. 300-303
• 
  Tan Yiyu, Yukinori Sato, Eiko Sugawara, Yasushi Inoguchi, Makoto Otani, Yukio Iwaya, Hiroshi Matsuoka, Takao Tsuchiya: A FPGA implementation of the two-dimensional Digital Huygens' Model. 304-307
• 
  Gavin Xiaoxu Yao, Ray C. C. Cheung, Çetin Kaya Koç, Kim Fung Man: Reconfigurable Number Theoretic Transform architectures for cryptographic applications. 308-311
• 
  Haile Yu, Philip Heng Wai Leong, Qiang Xu: An FPGA chip identification generator using configurable ring oscillator. 312-315
• 
  Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan: FPGA implementation of an interior point solver for linear model predictive control. 316-319
• 
  Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong: General switch box modeling and optimization for FPGA routing architectures. 320-323
• 
  Yi Lu, Koen Bertels, Georgi Gaydadjiev: Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems. 324-327
• 
  Bijan Alizadeh, Masahiro Fujita: A debugging method for repairing post-silicon bugs of high performance processors in the fields. 328-331

Poster Session

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  Jingchuan Wang, Weidong Chen: Integration of PSoC technology with educational robotics. 332-336
• 
  Guoqiang Wang, Trung N. Tran, Hugo A. Andrade: A graphical programming and design environment for FPGA-based hardware. 337-340
• 
  Yousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron D. Patterson: Using partial reconfiguration and high-level models to accelerate FPGA design validation. 341-344
• 
  Benjamin Kwek, Freddie Sunarso, Melissa Teoh, Arrian van Zal, Philip Preston, Oliver Diessel: FPGA-based video processing for a vision prosthesis. 345-348
• 
  Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano: Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. 349-352
• 
  Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings: Rapid prototyping tools for FPGA designs: RapidSmith. 353-356
• 
  Toktam Taghavi, Andy D. Pimentel: VMODEX: A visualization tool for multi-objective Design Space Exploration. 357-360
• 
  Dirk Koch, Christian Beckhoff, Jim Tørresen: Advanced partial run-time reconfiguration on Spartan-6 FPGAs. 361-364
• 
  Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, Yajun Ha: Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. 365-368

Poster Session

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  Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So: Design space exploration for sparse matrix-matrix multiplication on FPGAs. 369-372
• 
  Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaïane: Accelerating FPGA design space exploration using circuit similarity-based placement. 373-376
• 
  Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun: Structured ASIC: Methodology and comparison. 377-380
• 
  Glen Gibb, Nick McKeown: OpenPipes: Making distributed hardware systems easier. 381-384
• 
  Kaveh Aasaraai, Andreas Moshovos: Design space exploration of instruction schedulers for out-of-order soft processors. 385-388
• 
  Zhiyao Joseph Yang, Akash Kumar, Yajun Ha: An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee. 389-392
• 
  Fakhar Anjam, Muhammad Nadeem, Stephan Wong: A VLIW softcore processor with dynamically adjustable issue-slots. 393-398
• 
  Shuichi Asano, Zheng Zhi Shun, Tsutomu Maruyama: An FPGA implementation of full-search variable block size motion estimation. 399-402
• 
  Fakhar Anjam, Stephan Wong, Faisal Nadeem: A multiported register file with register renaming for configurable softcore VLIW processors. 403-408
• 
  Eric Matthews, Lesley Shannon, Alexandra Fedorova: A configurable framework for investigating workload execution. 409-412
• 
  Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan: Performance estimation framework for FPGA-based processors. 413-416
• 
  Michitarou Yabuuchi, Kazutoshi Kobayashi: Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations. 417-420
• 
  Donald G. Bailey: Efficient implementation of greyscale morphological filters. 421-424
• 
  Andrew van der Byl, Michael R. Inggs, Richardt H. Wilkinson: A many processing element framework for the Discrete Fourier Transform. 425-428
• 
  Kyuseung Han, Jong Kyung Paek, Kiyoung Choi: Acceleration of control flow on CGRA using advanced predicated execution. 429-432

Design Competition

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  Xiaojun Yang, Christoforos Kachris, Manolis Katevenis: Efficient implementation of CIOQ switches with sequential iterative matching algorithms. 433-436
• 
  João Bispo, João M. P. Cardoso: On identifying and optimizing instruction sequences for dynamic compilation. 437-440
• 
  Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri: A datapath classification method for FPGA-based scientific application accelerator systems. 441-444
• 
  Huynh Phung Huynh, Yun Liang, Tulika Mitra: Efficient custom instructions generation for system-level design. 445-448
• 
  Suhaib A. Fahmy: Histogram-based probability density function estimation on FPGAs. 449-453
• 
  Zubair Nawaz, Muhammad Nadeem, Hans van Someren, Koen Bertels: A parallel FPGA design of the Smith-Waterman traceback. 454-459
• 
  Dirk Koch, Jim Tørresen: Routing optimizations for component-based system design and partial run-time reconfiguration on FPGAs. 460-464
• 
  Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek: Solving Sudokus through an incidence matrix on an FPGA. 465-469
• 
  Pavlos Malakonakis, Euripides Sotiriades, Apostolos Dollas: GE3: A single FPGA client-server architecture for Golomb Ruler derivation. 470-473
• 
  Sascha Mühlbach, Andreas Koch: An FPGA-based scalable platform for high-speed malware collection in large IP networks. 474-478
• 
  Xuezheng Chu, John McAllister: FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case study. 479-484
• 
  Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger: A deeply pipelined and parallel architecture for denoising medical images. 485-490
• 
  Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita: SEU tolerant SRAM for FPGA applications. 491-494
• 
  Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk: Convex models for accelerating applications on FPGA-based clusters. 495-498
• 
  Yuichiro Yamaji, Minoru Watanabe: A 64-context MEMS optically reconfigurable gate array. 499-502
• 
  Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev: Minimalistic architecture for reconfigurable audio Beamforming. 503-506

Design Competition

• 
  Javier Olivito, Carlos González, Javier Resano: FPGA implementation of a strong Reversi player. 507-510
• 
  Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe: Othello Solver based on a soft-core MIMD processor array. 511-514
• 
  Miltiadis Smerdis, Pavlos Malakonakis, Apostolos Dollas: CarlOthello : An FPGA-Based Monte Carlo Othello player. 515-518

last updated on Mon May 20 01:59:59 2013 by the dblp team
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