ESSCIRC 2011: Helsinki, Finland

• Pierre Dautriche:
  Analog design trends and challenges in 28 and 20nm CMOS technology. 1-4
  
• Paul Heremans, Wim Dehaene, Michiel Steyaert, Kris Myny, Hagen Marien, Jan Genoe, Gerwin H. Gelinck, Erik van Veenendaal:
  Circuit design in organic semiconductor technologies. 5-12
  
• Laurent Fulbert, Jean-Marc Fedeli:
  Photonics - Electronics integration on CMOS. 13-18
  
• Jan M. Rabaey:
  Brain-machine interfaces as the new frontier in extreme miniaturization. 19-24
  
• Aarno Pärssinen:
  Multimode-multiband transceivers for next generation of wireless communications. 25-36
  
• Peter D. Bradley:
  Wireless medical implant technology - Recent advances and future developments. 37-41
  
• Michiel Steyaert, Tom Van Breussegem, Hans Meyvaert, Piet Callemeyn, Mike Wens:
  DC-DC converters: From discrete towards fully integrated CMOS. 42-49
  
• Martin M. Frank:
  High-k/metal gate innovations enabling continued CMOS scaling. 50-58
  
• Alan C. Seabaugh:
  Fundamentals and current status of steep-slope tunnel field-effect transistors. 59-60
  
• Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda:
  Current status on GaN-based RF-power devices. 61-66
  
• Jonathan Müller, Bruno Stefanelli, Antoine Frappe, Lu Ye, Andreia Cathelin, Ali M. Niknejad, Andreas Kaiser:
  A 7-bit 18^th order 9.6 GS/s FIR filter for high data rate 60-GHz wireless communications. 67-70
  
• Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
  A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. 71-74
  
• Matthias Korb, Tobias G. Noll:
  Area- and energy-efficient high-throughput LDPC decoders with low block latency. 75-78
  
• Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
  A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. 79-82
  
• Amit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy:
  A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. 83-86
  
• Marco Berkhout, Lutsen Dooper:
  A 3.4W digital-in class-D audio amplifier. 87-90
  
• Davide Cartasegna, Piero Malcovati, Lorenzo Crespi, Kyehyung Lee, Lakshmi Murukutla, Andrea Baschirotto:
  An audio 91-dB THD third-order fully-differential class-D amplifier. 91-94
  
• Yasuhiro Sugimoto:
  Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS. 95-98
  
• Alberto Villegas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda:
  A 3.6mW @ 1.2V high linear 8^th-order CMOS complex filter for IEEE 802.15.4 standard. 99-102
  
• Pieter Harpe, Cui Zhou, Kathleen Philips, Harmke de Groot:
  A 1.6mW 0.5GHz open-loop VGA with fast startup and offset calibration for UWB radios. 103-106
  
• Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato:
  A 100m-range 10-frame/s 340×96-pixel time-of-flight depth sensor in 0.18μm CMOS. 107-110
  
• Andreas Spickermann, Daniel Durini, Andreas Suss, Wiebke Ulfig, Werner Brockherde, Bedrich J. Hosticka, Stefan Schwope, Anton Grabmaier:
  CMOS 3D image sensor based on pulse modulated time-of-flight principle and intrinsic lateral drift-field photodiode pixels. 111-114
  
• Jian Guo, Sameer Sonkusale:
  A CMOS imager with digital phase readout for fluorescence lifetime imaging. 115-118
  
• Shingo Mandai, Edoardo Charbon:
  A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imaging. 119-122
  
• Rainer Krenzke, Cang Ji:
  A 140 dB equivalent dynamic range receiver interface for an infrared rain-sensing IC. 123-126
  
• Jonas Fritzin, Christer Svensson, Atila Alvandpour:
  A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE. 127-130
  
• Wei Tai, Hongtao Xu, Ashoke Ravi, Hasnain Lakdawala, Ofir B. Degani, L. Richard Carley, Yorgos Palaskas:
  A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control. 131-134
  
• Ercan Kaymaksut, Patrick Reynaert:
  CMOS transformer-based uneven Doherty power amplifier for WLAN applications. 135-138
  
• Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels:
  A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. 139-142
  
• Hugo Veenstra, Marc Notten, Dixian Zhao, John R. Long:
  A 3-channel true-time delay transmitter for 60GHz radar-beamforming applications. 143-146
  
• Pieter Harpe, Ben Busze, Kathleen Philips, Harmke de Groot:
  A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios. 147-150
  
• Stefano D'Amico, Giuseppe Cocciolo, Marcello De Matteis, Andrea Baschirotto:
  A 7.65mW 5bits 90nm 1Gs/s ADC folded-interpolated without calibration. 151-154
  
• Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou:
  A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. 155-158
  
• Nathan Ickes, Yildiz Sinangil, Francesco Pappalardo, Elio Guidetti, Anantha P. Chandrakasan:
  A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip. 159-162
  
• Eduard Roytman, Mali Nagarajan, Rahul Shah, Xin Ma, Ronald Bedard, Kambiz Munshi, Russell Iknaian, Fengxiang Cai, Jian Xu, Gayathri Sridharan Devi, Pradeep Vempada:
  Variation tolerant digitally assisted high-speed IO PHY. 163-166
  
• Arnoud P. van der Wel, Gerrit den Besten:
  A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS. 167-170
  
• Jongmoon Kim, Seokoh Yun, Wonkap Oh, Minsu Kil, Sanghyun Cho:
  A true single SoC for UHF mobile RFID reader. 171-174
  
• Junhua Liu, Chen Li, Long Chen, Yehui Xiao, Jiayi Wang, Huailin Liao, Ru Huang:
  An ultra-low power 400MHz OOK transceiver for medical implanted applications. 175-178
  
• Jia Mao, David Sarmiento M., Qin Zhou, Jian Chen, Peng Wang, Zhuo Zou, Fredrik Jonsson, Li-Rong Zheng:
  A 90nm CMOS UHF/UWB asymmetric transceiver for RFID readers. 179-182
  
• Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
  On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. 183-186
  
• Sushrant Monga, Vinod Kumar:
  A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS. 187-190
  
• Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai:
  12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. 191-194
  
• Gerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl, Sylvia Michaelis, Dietrich Michaelis, Christoph Sandner:
  Fast and robust level shifters in 65 nm CMOS. 195-198
  
• Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
  A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. 199-202
  
• Fridolin Michel, Michiel Steyaert:
  Differential input topologies with immunity to electromagnetic interference. 203-206
  
• Faizah Abu Bakar, Tero Nieminen, Qaiser Nehal, Pekka Ukkonen, Ville Saari, Kari Halonen:
  Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver. 207-210
  
• Björn Eversmann, Armin Lambacher, Thomas Gerling, Alexander Kunze, Peter Fromherz, Roland Thewes:
  A neural tissue interfacing chip for in-vitro applications with 32k recording / stimulation channels on an active area of 2.6 mm². 211-214
  
• Xiao Liu, Andreas Demosthenous, Dai Jiang, Anne Vanhoestenberghe, Nick Donaldson:
  A stimulator ASIC with capability of neural recording during inter-phase delay. 215-218
  
• Wen-Sin Liew, Xiaodan Zou, Yong Lian:
  A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme. 219-222
  
• Karim Abdelhalim, Roman Genov:
  915-MHz wireless 64-channel neural recording SoC with programmable mixed-signal FIR filters. 223-226
  
• Jos Bergervoet, Domine Leenaerts, Gerben de Jong, Edwin van der Heijden, Jan-Willem Lobeek, A. Simin:
  A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe: C BiCMOS. 227-230
  
• Hemasundar M. Geddada, José Silva-Martínez, Stewart S. Taylor:
  Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS. 231-234
  
• Saul Rodriguez Duenas, Ana Rusu:
  A 6.4mW, 1-3.5GHz current-mode receiver front-end with noise cancellation. 235-238
  
• Maarten Tytgat, Michiel Steyaert, Patrick Reynaert:
  A 200GHz downconverter in 90nm CMOS. 239-242
  
• Elie Maricau, Georges G. E. Gielen:
  Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines. 243-246
  
• Pieter De Wit, Georges G. E. Gielen:
  A failure-resilient xDSL line driver with on-chip degradation monitor. 247-250
  
• Florian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel:
  An aging suppression and calibration approach for differential amplifiers in advanced CMOS technologies. 251-254
  
• Jason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle:
  Circuit-aware device reliability criteria methodology. 255-258
  
• Ankesh Jain, Muthusubramanian Venkateswaran, Shanthi Pavan:
  A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. 259-262
  
• Ahmed Ashry, Hassan Aboushady:
  A 4^th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC. 263-266
  
• Francesco Cannillo, Enrique Prefasi, Luis Hernández, Ernesto Pun, Refet Firat Yazicioglu, Chris Van Hoof:
  1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition. 267-270
  
• Blazej Nowacki, Nuno F. Paulino, João Goes:
  A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS. 271-274
  
• Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx:
  A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration. 275-278
  
• Kamran Souri, Youngcheol Chae, Youri Ponomarev, Kofi A. A. Makinwa:
  A precision DTMOST-based temperature sensor. 279-282
  
• Zhichao Tan, Michiel A. P. Pertijs, Gerard C. M. Meijer:
  An energy-efficient 15-bit capacitive sensor interface. 283-286
  
• Hans Danneels, Kristof Coddens, Georges G. E. Gielen:
  A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references. 287-290
  
• Mikail Yücetas, Lasse Aaltonen, Mika Pulkkinen, Jarno Salomaa, Antti Kalanti, Kari Halonen:
  A charge balancing accelerometer interface with electrostatic damping. 291-294
  
• Thomas Northemann, Rainer Schillinger, Michael Maurer, Yiannos Manoli:
  Controlling the primary mode of gyroscopes with a phase-based amplitude regulation. 295-298
  
• Jonas Lindstrand, Carl Bryant, Markus Tormanen, Henrik Sjöland:
  A 1.6-2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS. 299-302
  
• Brecht François, Patrick Reynaert:
  A fully integrated CMOS power amplifier for LTE-applications using clover shaped DAT. 303-306
  
• Liang Rong, Fredrik Jonsson, Li-Rong Zheng:
  A 11.4dBm 90nm CMOS H-Bridge resonating polar amplifier using RF Sigma Delta Modulation. 307-310
  
• Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun-Seong Eo, Huyn-Kyu Yu:
  A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip. 311-314
  
• Sylvain Jolivet, Sébastien Amiot, Olivier Crand, Simon Bertrand, Bernard Jarry, Julien Lintignat:
  A high dynamic range fully-active 45-240MHz tunable RF bandpass filter for TV tuners. 315-318
  
• Shagun Bajoria, Martijn F. Snoeij, Viola Schaffer, Mikhail V. Ivanov, Sijia Wang, Kofi A. A. Makinwa:
  A 36V voltage-to-current converter with dynamic element matching and auto-calibration for AC ripple reduction. 319-322
  
• Fausto Borghetti, Nicola Massari, David Stoppa, Andrea Adami, Leandro Lorenzelli, Franco Maloberti:
  An analog readout circuit with offset calibration for cantiliver-based DNA detection. 323-326
  
• Andrei Danchiv, Marian Hulub, Diana Manta:
  An area efficient multi-channel high side switch implementation. 327-330
  
• Iasonas F. Triantis, Andreas Demosthenous, Mohamad Rahal, Hongwei Hong, Richard H. Bayford:
  A multi-frequency bioimpedance measurement ASIC for electrical impedance tomography. 331-334
  
• Marco Guermandi, Roberto Cardu, Eleonora Franchi, Roberto Guerrieri:
  Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wire. 335-338
  
• Sun-Il Chang, Khaled Al-Ashmouny, Euisik Yoon:
  A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application. 339-342
  
• Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata:
  A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS. 343-346
  
• Olivier Jamin, Vincent Rambeau, Franck Goussin, Guillaume Lebailly:
  An RF front-end for multi-channel direct RF sampling cable receivers. 347-350
  
• Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang:
  A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. 351-354
  
• Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
  A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC. 355-358
  
• Ray Nguyen, Christine Raynaud, Andreia Cathelin, Boris Murmann:
  A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS. 359-362
  
• U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
  A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. 363-366
  
• Heng Zhang, Junhua Tan, Chao Zhang, Hongbo Chen, Edgar Sánchez-Sinencio:
  A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC. 367-370
  
• Thorsten Hehn, Dominic Maurath, Friedrich Hagedorn, Djordje Marinkovic, Ingo Kuehne, Alexander Frey, Yiannos Manoli:
  A fully autonomous pulsed synchronous charge extractor for high-voltage piezoelectric harvesters. 371-374
  
• Chia-Min Chen, Chung-Chih Hung:
  A fast self-reacting capacitor-less low-dropout regulator. 375-378
  
• Gerard Villar Pique, Maurice Meijer:
  A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias. 379-382
  
• Tzu-Chi Huang, Wen-Shen Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Yung-Chow Peng, Fu-Lung Hsueh:
  55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter. 383-386
  
• Ali Zahabi, Muhammad Anis, Maurits Ortmanns:
  3.1GHz-3.8GHz integrated transmission line super-regeneration amplifier with degenerative quenching technique for impulse-FM-UWB transceiver. 387-390
  
• Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis:
  A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. 391-394
  
• Pieter A. J. Nuyts, Peter Singerl, Franz Dielacher, Patrick Reynaert, Wim Dehaene:
  A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS. 395-398
  
• Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada:
  A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. 399-402
  
• Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, Chen-Yi Lee:
  A low power all-digital signal component separator for uneven multi-level LINC systems. 403-406
  
• Michael Georgas, Jason Orcutt, Rajeev J. Ram, Vladimir Stojanovic:
  A monolithically-integrated optical receiver in standard 45-nm SOI. 407-410
  
• Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans:
  DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil. 411-414
  
• Daniele Raiteri, Fabrizio Torricelli, Eugenio Cantatore, Arthur H. M. van Roermund:
  A tunable transconductor for analog amplification and filtering based on double-gate organic TFTs. 415-418
  
• Alessandro Cabrini, Fabio Gallazzi, Guido Torelli:
  Current reference scheme for multilevel phase-change memory sensing. 419-422
  
• Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, SangBum Kim, Jonathan Proesel, Chung Lam:
  Post-silicon calibration of analog CMOS using phase-change memory cells. 423-426
  
• Sebastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, Angelo Nagari:
  A 65-nm, 1-A buck converter with multi-function SAR-ADC-based CCM/PSK digital control loop. 427-430
  
• Chun-Jen Shih, Kuan-Yu Chu, Yu-Huei Lee, Ke-Horng Chen:
  Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converter. 431-434
  
• Weiwei Xu, Ye Li, Zhiliang Hong, Dirk Killat, Horst Schleifer:
  A single-inductor multiple-bipolar-output (SIMBO) converter with fully-adaptive feedback matrix and improved light-load ripple. 435-438
  
• Qadeer Khan, Sachin Rao, Damian Swank, Arun Rao, William McIntyre, Sarvesh Bang, Pavan Kumar Hanumolu:
  A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control. 439-442
  
• Lin Cheng, Jinhua Ni, Zhiliang Hong, Bill Yang Liu:
  A constant off-time controlled boost converter with adaptive current sensing technique. 443-446
  
• Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang:
  A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. 447-450
  
• Chun-Pang Wu, Sheng-Sian Wang, Hen-Wai Tsao, Jingshown Wu:
  A 300KHz bandwidth 3.9GHz 0.18μm CMOS fractional-N synthesizer with 13dB broadband phase noise reduction. 451-454
  
• Richard Su, Steven Lanzisera, Kristofer S. J. Pister:
  A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells. 455-458
  
• Ping Lu, Pietro Andreani, Antonio Liscidini:
  A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. 459-462
  
• Mathieu Egot, Baudouin Martineau, Olivier Richard, Nathalie Rolland, Andreia Cathelin, Andreas Kaiser:
  A 20-23GHz Coupled Oscillators Array in 65nm CMOS for HDR 60GHz beamforming applications. 463-466
  
• Dai Zhang, Ameya Bhide, Atila Alvandpour:
  A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices. 467-470
  
• Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro:
  A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. 471-474
  
• Chien-Hung Kuo, Cheng-En Hsieh:
  A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. 475-478
  
• Robert C. N. Pilawa-Podgurski, David J. Perreault:
  Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS. 479-482
  
• Hans Meyvaert, Tom Van Breussegem, Michiel Steyaert:
  A monolithic 0.77W/mm² power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS. 483-486
  
• Gerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl, Michael Wassermann, Andreas Petschar, Christoph Sandner:
  Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS. 487-490
  
• Lianming Li, Patrick Reynaert, Michiel Steyaert:
  A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques. 491-494
  
• Massoud Tohidian, Ali Fotowat-Ahmady, Mahmoud Kamarei, Fabien Ndagijimana:
  High-swing class-C VCO. 495-498
  
• Wei Deng, Kenichi Okada, Akira Matsuzawa:
  A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. 499-502
  
• Mahdi Kashmiri, Kamran Souri, Kofi A. A. Makinwa:
  A scaled thermal-diffusivity-based frequency reference in 0.16μm CMOS. 503-506
  
• Fabio Pareschi, Gianluca Setti, Riccardo Rovatti, Giovanni Frattini:
  A spread spectrum clock generator based on a short-term optimized chaotic map. 507-510
  
• Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta:
  Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS. 511-514
  
• Vadim Ivanov, Johannes Gerber, Ralf Brederlow:
  An ultra low power bandgap operational at supply as low as 0.75V. 515-518
  
• Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
  A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link. 519-522
  
• Anselme Vignon, Stefan Cosemans, Wim Dehaene:
  A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh. 523-526
  
• Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10^-19. 527-530
  
• Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
  8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes. 531-534
  
• Fabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt:
  A narrow-to-wideband scrambling technique increasing software radio receiver linearity. 535-538
  
• Mikko Kaltiokallio, Ville Saari, Jussi Ryynänen, Sami Kallioinen, Aarno Pärssinen:
  Wideband 2 to 6GHz RF front-end with blocker filtering. 539-542
  
• Xiongchuan Huang, Pieter Harpe, Guido Dolmans, Harmke de Groot:
  A 915MHz ultra-low power wake-up receiver with scalable performance and power consumption. 543-546
  
• Carl Bryant, Henrik Sjöland:
  A 65nm CMOS 282μW 915MHz direct conversion receiver front-end. 547-550
  
• Jong-Wook Lee, Duong Huynh Thai Vo, Sang-Hoon Hong, Quoc-Hung Huynh:
  A fully integrated high security NFC target IC using 0.18 μm CMOS process. 551-554
  

Last update Fri May 25 05:58:34 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page