"A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized ..."

Ryota Sekimoto et al. (2011)

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DOI: 10.1109/ESSCIRC.2011.6045009

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro:
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC 2011: 471-474

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