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Hyun-Kyu Yu
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2010 – 2019
- 2014
- [c10]Ja-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim:
A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm. MWSCAS 2014: 370-373 - 2013
- [j7]Sangjin Byun
, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu:
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. IET Circuits Devices Syst. 7(3) (2013) - 2012
- [j6]Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu:
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1706-1719 (2012) - 2011
- [c9]Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun Seong Eo, Hyun-Kyu Yu:
A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip. ESSCIRC 2011: 311-314 - [c8]Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC 2011: 176-178
2000 – 2009
- 2008
- [j5]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun
, Hyun-Kyu Yu:
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 43(2): 541-549 (2008) - 2006
- [j4]Sangjin Byun
, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. IEEE J. Solid State Circuits 41(11): 2566-2576 (2006) - [c7]Young-Jae Lee, Hyun-Kyu Yu:
A transformer-based low phase noise and widely tuned CMOS quadrature VCO. ISCAS 2006 - [c6]Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. ISSCC 2006: 1324-1333 - [c5]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. ISSCC 2006: 2152-2159 - 2005
- [c4]Young-Ho Kim, Hyun-Kyu Yu:
Automatic tuning circuit for Gm-C filters. ICECS 2005: 1-4 - 2004
- [j3]Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu:
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. IEEE J. Solid State Circuits 39(5): 761-774 (2004) - [j2]Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu:
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. IEEE J. Solid State Circuits 39(6): 871-884 (2004) - [c3]Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu:
A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order Chebyshev low pass filter. CICC 2004: 53-56 - 2002
- [c2]Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu:
A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA). ISCAS (3) 2002: 89-92 - [c1]Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu:
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. ISCAS (5) 2002: 373-376
1990 – 1999
- 1999
- [j1]Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim:
A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. IEEE Trans. Consumer Electron. 45(1): 171-175 (1999)
Coauthor Index
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