CASES 2007: Salzburg, Austria

• Walid A. Najjar:
  Compiling code accelerators for FPGAs. 1-2
  

Embedded development tools

• Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  A fast and generic hybrid simulation approach using C virtual machine. 3-12
  
• Florian Brandner, Dietmar Ebner, Andreas Krall:
  Compiler generation from structural architecture descriptions. 13-22
  
• Hugo Venturini, Frédéric Riss, Jean-Claude Fernandez, Miguel Santana:
  Non-transparent debugging for software-pipelined loops. 23-32
  

Short presentations with posters

• Sharad Singhai, MingYung Ko, Sanjay Jinturkar, Mayan Moudgill, John Glossner:
  An integrated ARM and multi-core DSP simulator. 33-37
  
• Raimund Kirner:
  SCCP/x: a compilation profile to support testing and verification of optimized code. 38-42
  
• Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley:
  Performance-driven syntax-directed synthesis of asynchronous processors. 43-47
  
• Stefan Schäckeler, Weijia Shang:
  Stack size reduction of recursive programs. 48-52
  
• Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha:
  Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems. 53-57
  
• Syed Imtiaz Haider, Leyla Nazhandali:
  A hybrid code compression technique using bitmask and prefix encoding with enhanced dictionary selection. 58-62
  

Scratchpad memories

• Kevin K. O'Brien:
  Techniques for code and data management in the local stores of the cell processor. 63-64
  
• Angel Dominguez, Nghi Nguyen, Rajeev Barua:
  Recursive function data allocation to scratch-pad memory. 65-74
  
• José Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, Jonathan Misurda:
  Fragment cache management for dynamic binary translators in embedded systems with scratchpad. 75-84
  
• Nghi Nguyen, Angel Dominguez, Rajeev Barua:
  Scratch-pad memory allocation without compiler support for java applications. 85-94
  

Applications

• Greg Hoover, Forrest Brewer, Timothy Sherwood:
  Towards understanding architectural tradeoffs in MEMS closed-loop feedback control. 95-102
  
• Karthik Ramani, Al Davis:
  Application driven embedded system design: a face recognition case study. 103-114
  
• Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge:
  Hierarchical coarse-grained stream compilation for software defined radio. 115-124
  

Instruction-set extension

• Ajay K. Verma, Philip Brisk, Paolo Ienne:
  Rethinking custom ISE identification: a new processor-agnostic method. 125-134
  
• Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra:
  An efficient framework for dynamic reconfiguration of instruction-set customization. 135-144
  

Short presentations with posters

• Andrea Marongiu, Luca Benini, Mahmut T. Kandemir:
  Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. 145-149
  
• Chengmo Yang, Alex Orailoglu:
  Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. 150-154
  
• Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir:
  Supporting multithreading in configurable soft processor cores. 155-159
  
• Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jinsoo Kim, Joonwon Lee:
  A group-based wear-leveling algorithm for large-capacity flash memory storage systems. 160-164
  
• Chris Zimmer, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley:
  Facilitating compiler optimizations through the dynamic mapping of alternate register structures. 165-169
  

Memory systems

• Ben Titzer, Jens Palsberg:
  Vertical object layout and compression for fixed heaps. 170-178
  
• Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek:
  Software controlled memory layout reorganization for irregular array access patterns. 179-188
  
• Weixing Ji, Feng Shi, Baojun Qiao:
  A self-maintained memory module supporting DMM. 189-197
  
• Rakesh Reddy, Peter Petrov:
  Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. 198-207
  
• Trevor N. Mudge:
  Multicore architectures. 208
  

Compilation/code generation

• Philip Brisk, Ajay K. Verma, Paolo Ienne:
  An optimistic and conservative register assignment heuristic for chordal graphs. 209-217
  
• Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum:
  A simplified java bytecode compilation system for resource-constrained embedded processors. 218-228
  
• Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter:
  A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. 229-237
  

Low power and thermal-aware architectures

• Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant:
  INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. 238-247
  
• Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen:
  Cache leakage control mechanism for hard real-time systems. 248-256
  
• Ravishankar Rao, Sarma B. K. Vrudhula:
  Performance optimal processor throttling under thermal constraints. 257-266
  
• Ahmad Zmily, Christos Kozyrakis:
  A low power front-end for embedded processors using a block-aware instruction set. 267-276
  

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