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Publication search results
found 65 matches
- 2009
- Cristinel Ababei:
Parallel placement for FPGAs revisited. FPGA 2009: 280 - Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani:
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. FPGA 2009: 281 - Jason Helge Anderson:
Emerging application domains: research challenges and opportunities for FPGAs. FPGA 2009: 1-2 - Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent:
Customizable bit-width in an OpenMP-based circuit design tool. FPGA 2009: 278 - Ray Bittner:
Bus mastering PCI express in an FPGA. FPGA 2009: 273-276 - Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs. FPGA 2009: 286 - Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin:
Automatic bus macro placement for partially reconfigurable FPGA designs. FPGA 2009: 269-272 - Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang:
A comparison of via-programmable gate array logic cell circuits. FPGA 2009: 53-62 - Sumanta Chaudhuri:
Diagonal tracks in FPGAs: a performance evaluation. FPGA 2009: 245-248 - Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 - Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner:
Fpga-based face detection system using Haar classifiers. FPGA 2009: 103-112 - Yee Jern Chong, Sri Parameswaran:
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. FPGA 2009: 171-180 - Jason Cong, Karthik Gururaj, Guoling Han:
Synthesis of reconfigurable high-performance multicore systems. FPGA 2009: 201-208 - Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou:
Revisiting bitwidth optimizations. FPGA 2009: 278 - Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang:
Computation reuse in domain-specific optimization of signal recognition. FPGA 2009: 281 - Süleyman Sirri Demirsoy, Martin Langhammer:
Cholesky decomposition using fused datapath synthesis. FPGA 2009: 241-244 - Florian Dittmann, Elmar Weber, Norma Montealegre:
Implementation of the reconfiguration port scheduling on the erlangen slot machine. FPGA 2009: 282 - Chen Dong, Scott Chilstedt, Deming Chen:
FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170 - Claudio Favi, Edoardo Charbon:
A 17ps time-to-digital converter implemented in 65nm FPGA technology. FPGA 2009: 113-120 - Rosemary M. Francis, Simon W. Moore:
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. FPGA 2009: 285 - Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck:
SPR: an architecture-adaptive CGRA mapping tool. FPGA 2009: 191-200 - Kanupriya Gulati, Sunil P. Khatri, Peng Li:
Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287 - Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt:
FPGA-based front-end electronics for positron emission tomography. FPGA 2009: 93-102 - Johnny Tsung Lin Ho, Guy G. Lemieux:
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260 - Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240 - Weirong Jiang, Viktor K. Prasanna:
Large-scale wire-speed packet classification on FPGAs. FPGA 2009: 219-228 - Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon:
FPGA implementation of real-time skin color detection with mean-based surface flattening. FPGA 2009: 283 - Server Kasap, Khaled Benkrid, Ying Liu:
A high performance fpga-based implementation of position specific iterated blast. FPGA 2009: 249-252 - Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox:
FPGA technology mapping with encoded libraries andstaged priority cuts. FPGA 2009: 143-150
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