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Publication search results
found 43 matches
- 2010
- Kahraman D. Akdemir, Berk Sunar:
Generic approach for hardening state machines against strong adversaries. IET Comput. Digit. Tech. 4(6): 458-470 (2010) - Ahmed K. Al-Sulaifanie, Arash Ahmadi, Mark Zwolinski:
Very large scale integration architecture for integer wavelet transform. IET Comput. Digit. Tech. 4(6): 471-483 (2010) - Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. IET Comput. Digit. Tech. 4(2): 104-113 (2010) - Abdelhafid Bouhraoua:
Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine. IET Comput. Digit. Tech. 4(4): 334-348 (2010) - Zhen Chen, J. Feng, Dong Xiang, Boxue Yin:
Scan chain configuration based X-filling for low power and high quality testing. IET Comput. Digit. Tech. 4(1): 1-13 (2010) - Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai:
Low power design of phase-change memory based on a comprehensive model. IET Comput. Digit. Tech. 4(4): 285-292 (2010) - Jih-Ching Chiu, Ta-Li Yeh:
IRES: An integrated software and hardware interface framework for reconfigurable embedded system. IET Comput. Digit. Tech. 4(1): 27-37 (2010) - J. Choi, H. Cha:
System-level power management for system-on-a-chip -based mobile devices. IET Comput. Digit. Tech. 4(5): 400-409 (2010) - Santanu Kumar Dash, Thambipillai Srikanthan:
Instruction cache tuning for embedded multitasking applications. IET Comput. Digit. Tech. 4(6): 439-457 (2010) - Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang:
Output remapping technique for critical paths soft-error rate reduction. IET Comput. Digit. Tech. 4(4): 325-333 (2010) - Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. IET Comput. Digit. Tech. 4(6): 499-514 (2010) - Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan:
Skew compensation in energy recovery clock distribution networks. IET Comput. Digit. Tech. 4(1): 56-72 (2010) - Bo Fu, Paul Ampadu:
Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. IET Comput. Digit. Tech. 4(3): 251-261 (2010) - Yoann Guillemenet, Lionel Torres, Gilles Sassatelli:
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. IET Comput. Digit. Tech. 4(3): 211-226 (2010) - Michael Higgins, Ciaran MacNamee, Brendan Mullane:
Design and implementation challenges for adoption of the IEEE 1500 standard. IET Comput. Digit. Tech. 4(1): 38-49 (2010) - B. A. Al Jassani, Neil Urquhart, A. E. A. Almaini:
Manipulation and optimisation techniques for Boolean logic. IET Comput. Digit. Tech. 4(3): 227-239 (2010) - Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi:
Low-power dual-edge triggered state-retention scan flip-flop. IET Comput. Digit. Tech. 4(5): 410-419 (2010) - Udo Kebschull, Marco Platzner, Jürgen Teich:
Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]. IET Comput. Digit. Tech. 4(3): 157-158 (2010) - Jong-Myon Kim, Sung Woo Chung, Cheol Hong Kim:
Energy-aware instruction cache design using small trace cache. IET Comput. Digit. Tech. 4(4): 293-305 (2010) - Ming-che Lai, Lei Gao, Zhiying Wang:
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains. IET Comput. Digit. Tech. 4(5): 374-387 (2010) - Feng Liu, Qingping Tan, Gang Chen, Xiaoyu Song, Otmane Aït Mohamed, Ming Gu:
Field programmable gate array prototyping of end-around carry parallel prefix tree architectures. IET Comput. Digit. Tech. 4(4): 306-316 (2010) - Liang Lu, John V. McCanny, Sakir Sezer:
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Comput. Digit. Tech. 4(5): 349-364 (2010) - Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan:
A Galois field-based logic synthesis with testability. IET Comput. Digit. Tech. 4(4): 263-273 (2010) - Aissa Melouki, Saket Srivastava, Bashir M. Al-Hashimi:
Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. IET Comput. Digit. Tech. 4(3): 240-250 (2010) - Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey:
Test pattern generation for droop faults. IET Comput. Digit. Tech. 4(4): 274-284 (2010) - Máire O'Neill, Matthew J. B. Robshaw:
Low-cost digital signature architecture suitable for radio frequency identification tags. IET Comput. Digit. Tech. 4(1): 14-26 (2010) - David O'Sullivan, Donal Heffernan:
VHDL architecture for IEC 61499 function blocks. IET Comput. Digit. Tech. 4(6): 515-524 (2010) - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra. IET Comput. Digit. Tech. 4(6): 484-498 (2010) - Irith Pomeranz, Sudhakar M. Reddy:
Diagnosis of path delay faults based on low-coverage tests. IET Comput. Digit. Tech. 4(2): 89-103 (2010) - Irith Pomeranz, Sudhakar M. Reddy:
Static test compaction for diagnostic test sets of full-scan circuits. IET Comput. Digit. Tech. 4(5): 365-373 (2010)
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