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Publication search results
found 46 matches
- 2003
- Reinaldo A. Bergamaschi, Grant Martin:
System-level design tools: who needs them, who has them, and how much should they cost? CODES+ISSS 2003: 79-80 - Reinaldo A. Bergamaschi, Grant Martin, Wayne H. Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris:
The future of system-level design: can we find the right solutions to the right problems at the right time? CODES+ISSS 2003: 231 - Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal:
SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155 - Doug Burger:
Architectural versus physical solutions for on-chip communication challenges. CODES+ISSS 2003: 74 - Lukai Cai, Daniel Gajski:
Transaction level modeling: an overview. CODES+ISSS 2003: 19-24 - Raul Camposano, Mark Underseth, Faraydon Karim:
Industry best practices in embedded software. CODES+ISSS 2003: 72-73 - Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
On-chip communication design: roadblocks and avenues. CODES+ISSS 2003: 75-76 - Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko:
Tracking object life cycle for leakage energy optimization. CODES+ISSS 2003: 213-218 - Mojy C. Chian:
Driving forces behind SOC development. CODES+ISSS 2003: 81 - Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78 - Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh:
First results with eBlocks: embedded systems building blocks. CODES+ISSS 2003: 168-175 - Nikil D. Dutt, Janos Sztipanovits, Masaki Hirata:
Driving agenda for systems research. CODES+ISSS 2003: 82 - Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel:
A multiobjective optimization model for exploring multiprocessor mappings of process networks. CODES+ISSS 2003: 182-187 - William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza:
Early estimation of the size of VHDL projects. CODES+ISSS 2003: 207-212 - Björn Franke, Michael F. P. O'Boyle:
Compiler parallelization of C programs for multi-core DSPs with multiple address spaces. CODES+ISSS 2003: 219-224 - Catherine H. Gebotys, Y. Zhang:
Security wrappers and power analysis for SoC technologies. CODES+ISSS 2003: 162-167 - Eike Grimpe, Frank Oppenheimer:
Extending the SystemC synthesis subset by object-oriented features. CODES+ISSS 2003: 25-30 - Andreas Hagen, Daniel A. Connors, Bryan L. Pellom:
The analysis and design of architecture systems for speech recognition on modern handheld-computing devices. CODES+ISSS 2003: 65-70 - Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
VL-CDRAM: variable line sized cached DRAMs. CODES+ISSS 2003: 132-137 - Pao-Ann Hsiung, Cheng-Yi Lin:
Synthesis of real-time embedded software with local and global deadlines. CODES+ISSS 2003: 114-119 - Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Schedule-aware performance estimation of communication architecture for efficient design space exploration. CODES+ISSS 2003: 195-200 - Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 - Paul Kohout, Brinda Ganesh, Bruce L. Jacob:
Hardware support for real-time operating systems. CODES+ISSS 2003: 45-51 - Arezou Koohi, Nader Bagherzadeh, Chengzi Pan:
A fast parallel reed-solomon decoder on a reconfigurable architecture. CODES+ISSS 2003: 59-64 - Wei Ming Lim, Mohammed Benaissa:
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography. CODES+ISSS 2003: 53-58 - James Lin:
Design technology challenges for system and chip level designs in very deep submicron technologies. CODES+ISSS 2003: 194 - Rafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, Harm Peters, Steffen Maul, Marcel Oosterhuis:
A low-cost and low-power multi-standard video encoder. CODES+ISSS 2003: 97-102 - Roman L. Lysecky, Frank Vahid:
A codesigned on-chip logic minimizer. CODES+ISSS 2003: 109-113 - Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi:
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. CODES+ISSS 2003: 103-108 - Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury:
Accurate estimation of cache-related preemption delay. CODES+ISSS 2003: 201-206
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