- Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, C. W. Liu:
First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61mV/dec, Ioff<10-7 μA/μm, DIBL =44mV/V, Positive VT, and Process Temp. of 300 °C. VLSI Technology and Circuits 2023: 1-2 - Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi:
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits 2023: 1-2 - Jeongwon Choe, Youngjoo Lee:
A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology. VLSI Technology and Circuits 2023: 1-2 - Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, SeongHwan Cho, Taekwang Jang:
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. VLSI Technology and Circuits 2023: 1-2 - Kyu-Jin Choi, Seungnam Choi, Jae-Yoon Sim:
A 110dB-TCMRR TDM-based 8-Channel Noncontact ECG Recording IC with Suppression of Motion-Induced Coupling in PP. VLSI Technology and Circuits 2023: 1-2 - Norio Chujo, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson, Tomoji Nakamura, Takayuki Ohba:
Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy. VLSI Technology and Circuits 2023: 1-2 - Tuur Van Daele, Filip Tavernier:
A Fully Integrated 230 VRMS-to-12 VDC AC-DC Converter Achieving 9 mW/mm2. VLSI Technology and Circuits 2023: 1-2 - Yaxin Ding, Jianguo Yang, Yu Liu, Jianfeng Gao, Yuan Wang, Pengfei Jiang, Shuxian Lv, Yuting Chen, Boping Wang, Wei Wei, Tiancheng Gong, Kanhao Xue, Qing Luo, Xiangshui Miao, Ming Liu:
16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells. VLSI Technology and Circuits 2023: 1-2 - Zuoyuan Dong, Zixuan Sun, Xin Yang, Xiaomei Li, Yongkang Xue, Chen Luo, Puyang Cai, Zirui Wang, Shuying Wang, Yewei Zhang, Chaolun Wang, Pengpeng Ren, Zhigang Ji, Xing Wu, Runsheng Wang, Ru Huang:
Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence. VLSI Technology and Circuits 2023: 1-2 - Shiro Dosho, Ludovico Minati, Kazuki Maari, Hiroyuki Ito:
A Compact 0.9uW Direct-Conversion Frequency Analyzer for Speech Recognition with Wide-Range Q-Controlable Bandpass Rectifier. VLSI Technology and Circuits 2023: 1-2 - Yiwei Du, Jianshi Tang, Yijun Li, Yue Xi, Bin Gao, He Qian, Huaqiang Wu:
Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture. VLSI Technology and Circuits 2023: 1-2 - Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers:
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits 2023: 1-2 - A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, R. Li, Iuliana P. Radu, P. Van Dorpe, Kristiaan De Greve:
Comprehensive 300 mm process for Silicon spin qubits with modular integration. VLSI Technology and Circuits 2023: 1-2 - Qiang Fang, Longyang Lin, Hui Zhang, Tianqi Wang, Massimo Alioto:
Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling. VLSI Technology and Circuits 2023: 1-2 - Luigi Fassio, Orazio Aiello, Massimo Alioto:
38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems. VLSI Technology and Circuits 2023: 1-2 - Mahdi Forghani, Yu Zhao, Pawan K. Khanna, Behzad Razavi:
A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology. VLSI Technology and Circuits 2023: 1-2 - Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, S. Brus, Romain Ritzenthaler, E. Dentoni Litta, Kris Croes, Ben Kaczer, N. Horiguchi:
Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. VLSI Technology and Circuits 2023: 1-2 - Yutaro Fujisaki, Hidenobu Tsugawa, K. Sakai, H. Kumagai, R. Nakamura, Tomoharu Ogita, S. Endo, T. Iwase, H. Takase, K. Yokochi, S. Yoshida, S. Shimada, Y. Otake, T. Wakano, H. Hiyama, K. Hagiwara, M. Arakawal, S. Matsumotol, H. Maeda, K. Sugihara, K. Takabayashi, M. Ono, K. Ishibashi, K. Yamamoto:
A back-illuminated 6 μm SPAD depth sensor with PDE 36.5% at 940 nm via combination of dual diffraction structure and 2×2 on-chip lens. VLSI Technology and Circuits 2023: 1-2 - Mitsuya Fukazawa, Tetsuo Matsui:
A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer. VLSI Technology and Circuits 2023: 1-2 - Souvik Ghosh, Quentin Smets, S. Banerjee, Tom Schram, K. Kennes, R. Verheyen, P. Kumar, M.-E. Boulon, Benjamin Groven, H. M. Silva, S. Kundu, Daire Cott, Dennis Lin, P. Favia, T. Nuytten, A. Phommahaxay, Inge Asselberghs, C. De La Rosa, Gouri Sankar Kar, Steven Brems:
Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. VLSI Technology and Circuits 2023: 1-2 - Tiancheng Gong, Lihua Xu, Wei Wei, Pengfei Jiang, Peng Yuan, Bowen Nie, Yuanquan Huang, Yuan Wang, Yang Yang, Jianfeng Gao, Junfeng Li, Jun Luo, Lingfei Wang, Jianguo Yang, Qing Luo, Ling Li, Steve S. Chung, Ming Liu:
First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip. VLSI Technology and Circuits 2023: 1-2 - N. Grossier, Fabio Disegni, A. Ventre, A. Barcella, R. Mariani, V. Marino, S. Mazzara, A. Scavuzzo, M. Bansal, B. Soni, A. Anand, S. Banzal, D. Joshi, R. Narwal, M. Niranjani, K. Trivedi, P. Ferreira, Rossella Ranica, L. Vullo, Andreia Cathelin, Alfonso Maurelli, S. Pezzini, M. Peri:
ASIL-D automotive-grade microcontroller in 28nm FD-SOI with full-OTA capable 21MB embedded PCM memory and highly scalable power management. VLSI Technology and Circuits 2023: 1-2 - P. Guo, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johannes G. Bosch, Nico de Jong, Martin D. Verweij, Michiel A. P. Pertijs:
A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. VLSI Technology and Circuits 2023: 1-2 - Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits 2023: 1-2 - Dongwan Ha, Ruida Yun, Kevin R. Wrenner:
A 0.22mm2 per Channel Data Link for Reinforced Isolation with >25kVpk Surge Tolerance and >295kV/μs Common Mode Transient Immunity. VLSI Technology and Circuits 2023: 1-2 - Walid M. Hafez, P. Agnihotri, M. Asoro, M. Aykol, B. Bains, R. Bambery, M. Bapna, A. Barik, A. Chatterjee, P. C. Chiu, T. Chu, C. Firby, K. Fischer, M. Fradkin, Hannes Greve, A. Gupta, E. Haralson, M. Haran, Jeffery Hicks, A. Illa, M. Jang, S. Klopcic, M. Kobrinsky, B. Kuns, H.-h. Lai, G. Lanni, S.-H. Lee, N. Lindert, C.-l. Lo, Y. Luo, G. Malyavanatham, B. Marinkovic, Y. Maymon, M. Nabors, J. Neirynck, P. Packan, A. Paliwal, L. Pantisano, Leif Paulson, Padma Penmatsa, Chetan Prasad, Conor Puls, T. Rahman, R. Ramaswamy, S. Samant, Bernhard Sell, K. Sethi, F. Shah, M. Shamanna, K. Shang, Q. Li, M. Sibakoti, J. Stoeger, N. Strutt, R. Thirugnanasambandam, C. Tsai, X. Wang, A. Wang, S.-j. Wu, Q. Xu, X.-h. Zhong, S. Natarajan:
Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing. VLSI Technology and Circuits 2023: 1-2 - Hyeonho Han, Woojun Choi, Jaehyun Kim, Jaesuk Sung, Heonjin Choi, Youngcheol Chae:
A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution. VLSI Technology and Circuits 2023: 1-2 - Kaizhen Han, Yuye Kang, Yue Chen, Xiao Gong:
Novel Bridge Transmission Line Method for Thin-Film Semiconductors: Modelling, Simulation Verification, and Experimental Demonstration. VLSI Technology and Circuits 2023: 1-2 - Jung-Won Han, S. H. Park, M. Y. Jeong, K. S. Lee, K. N. Kim, H. J. Kim, J. C. Shin, S. M. Park, S. H. Shin, S. W. Park, K. S. Lee, J. H. Lee, S. H. Kim, B. C. Kim, M. H. Jung, I. Y. Yoon, H. Kim, S. U. Jang, K. J. Park, Y. K. Kim, I. G. Kim, J. H. Oh, S. Y. Han, B. S. Kim, B. J. Kuh, J. M. Park:
Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -. VLSI Technology and Circuits 2023: 1-2 - Yi Han, Jingxuan Sun, Jin Hee Bae, Detlev Grützmacher, Joachim Knoch, Qing-Tai Zhao:
High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain. VLSI Technology and Circuits 2023: 1-2