- Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu:
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. Asian Test Symposium 2013: 159-164 - Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang:
Scan Test Data Volume Reduction for SoC Designs in EDT Environment. Asian Test Symposium 2013: 103-104 - Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
A New LFSR Reseeding Scheme via Internal Response Feedback. Asian Test Symposium 2013: 97-102 - Long-Yi Lin, Hao-Chiao Hong:
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model. Asian Test Symposium 2013: 62-66 - Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium 2013: 1-6 - Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning:
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium 2013: 215-220 - Spencer K. Millican, Kewal K. Saluja:
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. Asian Test Symposium 2013: 165-170 - Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium 2013: 171-176 - Jose Moreira, Bernhard Roth, Hubert Werkmann, Lars Klapproth, Michael Howieson, Mark Broman, Wend Ouedraogo, Mitchell Lin:
An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System. Asian Test Symposium 2013: 271-276 - Masafumi Nikaido, Yukihisa Funatsu, Tetsuya Seiyama, Junpei Nonaka, Kazuki Shigeta:
Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors. Asian Test Symposium 2013: 67-72 - Peter Sarson, Gregor Schatzberger, Robert Seitz:
Automotive EEPROM Qualification and Cost Optimization. Asian Test Symposium 2013: 105-106 - Yasuo Sato, Seiji Kajihara:
A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium 2013: 183-188 - Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty:
Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium 2013: 43-48 - Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - Kun-Han Tsai, Xijiang Lin:
Multicycle-aware At-speed Test Methodology. Asian Test Symposium 2013: 49 - Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - Ran Wang, Krishnendu Chakrabarty, Bill Eklow:
Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs. Asian Test Symposium 2013: 147-152 - Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee:
Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements. Asian Test Symposium 2013: 56-61 - Dong Xiang:
A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing. Asian Test Symposium 2013: 207-212 - Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium 2013: 79-84 - Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li:
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. Asian Test Symposium 2013: 7-12 - Fangming Ye, Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu:
Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis. Asian Test Symposium 2013: 73-78 - Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh:
Digital Compensation for Timing Mismatches in Interleaved ADCs. Asian Test Symposium 2013: 134-139 - Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li:
Path Constraint Solving Based Test Generation for Hard-to-Reach States. Asian Test Symposium 2013: 239-244 - 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013. IEEE Computer Society 2013, ISBN 978-0-7695-5080-0 [contents]