- 1997
- Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC 1997: 625 - Karim Arabi, Bozena Kaminska:
Efficient and accurate testing of analog-to-digital converters using oscillation-test method. ED&TC 1997: 348-352 - Renate Beckmann, Jürgen Herrmann:
Using constraint logic programming in memory synthesis for general purpose computers. ED&TC 1997: 619 - Philippe Bénabès, Mansour Keramat, Richard Kielbasa:
A methodology for designing continuous-time sigma-delta modulators. ED&TC 1997: 46-50 - Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ED&TC 1997: 514-520 - Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar:
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565 - Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta:
An RTL methodology to enable low overhead combinational testing. ED&TC 1997: 146-152 - Ronald D. Blanton, John P. Hayes:
The input pattern fault model and its application. ED&TC 1997: 628 - Alessandro Bogliolo, Luca Benini, Giovanni De Micheli:
Adaptive least mean square behavioral power modeling. ED&TC 1997: 404-410 - Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
A novel methodology for designing TSC networks based on the parity bit code. ED&TC 1997: 440-444 - Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
Verification and synthesis of counters based on symbolic techniques. ED&TC 1997: 176-181 - Kanad Chakraborty, Pinaki Mazumder:
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. ED&TC 1997: 330-334 - Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Hybrid symbolic-explicit techniques for the graph coloring problem. ED&TC 1997: 422-426 - Hoon Choi, Seung Ho Hwang:
Improving the accuracy of support-set finding method for power estimation of combinational circuits. ED&TC 1997: 526-530 - Radim Cmar, Serge Vernalde:
Highly scalable parallel parametrizable architecture of the motion estimator. ED&TC 1997: 208-212 - Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
New static compaction techniques of test sequences for sequential circuits. ED&TC 1997: 37-43 - Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev:
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. ED&TC 1997: 98-105 - Olivier Coudert:
Solving graph optimization problems with ZBDDs. ED&TC 1997: 224-228 - Jim E. Crenshaw, Majid Sarrafzadeh:
Accurate high level datapath power estimation. ED&TC 1997: 590-596 - A. Dargelas, C. Gauthron, Yves Bertrand:
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. ED&TC 1997: 29-36 - Ali Dasdan, Anmol Mathur, Rajesh K. Gupta:
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. ED&TC 1997: 2-6 - Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven:
High-level synthesis of analog sensor interface front-ends. ED&TC 1997: 56-60 - Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker:
Testability of 2-level AND/EXOR circuits. ED&TC 1997: 548-553 - Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian:
Fault-secure shifter design: results and implementations. ED&TC 1997: 335-341 - Christian Dufaza, Yervant Zorian:
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC 1997: 69-76 - Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr:
A constructive approach towards correctness of synthesis-application within retiming. ED&TC 1997: 427-431 - Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser:
A new field programmable system-on-a-chip for mixed signal integration. ED&TC 1997: 610 - Michele Favalli, Cecilia Metra:
Testing scheme for IC's clocks. ED&TC 1997: 445-449 - John P. Fishburn:
Shaping a VLSI wire to minimize Elmore delay. ED&TC 1997: 244-251 - Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165