default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDKeishi Sakanushi
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
Journal Articles
- 2013
[j12]Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka:
Electronic triage system for continuously monitoring casualties at disaster scenes. J. Ambient Intell. Humaniz. Comput. 4(5): 547-558 (2013)- 2012
- [j11]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. IEICE Trans. Electron. 95-C(4): 487-494 (2012) - 2011
- [j10]Ittetsu Taniguchi
, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2659-2668 (2011) - 2010
- [j9]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). Inf. Media Technol. 5(4): 1064-1081 (2010) - [j8]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. Inf. Media Technol. 5(4): 1110-1121 (2010) - [j7]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. 3: 161-178 (2010) - [j6]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 3: 222-233 (2010) - 2009
- [j5]Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai:
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1088-1095 (2009) - [j4]Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3258-3267 (2009) - 2007
- [j3]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto:
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2800-2809 (2007) - 2003
- [j2]Kazuya Wakata, Hiroaki Saito, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata, Chikaaki Kodama:
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3148-3157 (2003) - 2002
- [j1]Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani:
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 872-879 (2002)
Conference and Workshop Papers
- 2012
- [c26]Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
On-chip Communication Buffer Architecture Optimization Considering Bus Width. MCSoC 2012: 29-36 - [c25]Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. MCSoC 2012: 107-112 - 2011
- [c24]Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka:
Electronic Triage System: Casualties Monitoring System in the Disaster Scene. 3PGCIC 2011: 317-322 - [c23]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato:
Biological information sensing technologies for medical, health care, and wellness applications. ASP-DAC 2011: 551-555 - [c22]Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Automated architecture exploration for low energy reconfigurable AGU. ISOCC 2011: 191-194 - 2010
- [c21]Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Two-stage configurable decoder model for multiple forward error correction standards. ESTIMedia 2010: 114-120 - [c20]Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. ISCAS 2010: 3729-3732 - 2009
- [c19]Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC 2009: 449-454 - 2007
- [c18]Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC 2007: 286-291 - [c17]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS 2007: 227-232 - [c16]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi:
A Block-Floating-Point Processor for Rapid Application Development. ICASSP (2) 2007: 65-68 - 2006
- [c15]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa:
Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS 2006: 154-159 - [c14]Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295 - [c13]Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai:
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. VLSI-SoC (Selected Papers) 2006: 357-376 - 2005
- [c12]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Enabling RTOS simulation modeling in a system level design language. ASP-DAC 2005: 936-939 - [c11]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE 2005: 554-559 - 2004
- [c10]Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC 2004: 842-845 - [c9]Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007 - [c8]H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops 2004: 824-830 - [c7]Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai:
S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) 2004: 505-508 - 2003
- [c6]Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani:
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. ASP-DAC 2003: 338-341 - [c5]Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai:
A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES 2003: 66-80 - 2002
- [c4]Hiroaki Saito, Kazuya Wakata, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata:
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. APCCAS (2) 2002: 125-130 - [c3]Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin:
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. DATE 2002: 61-68 - 1998
- [c2]Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani:
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274 - [c1]Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita:
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425
Informal and Other Publications
- 2007
- [i1]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. CoRR abs/0710.4746 (2007)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-06 00:40 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
