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"A linear model for high-level delay estimation in VDSM on-chip interconnects."

Alberto García Ortiz et al. (2005)

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DOI: 10.1109/ISCAS.2005.1464779

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/iscas/OrtizMPG05
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Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects. ISCAS (2) 2005: 1078-1081

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