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2020 – today
- 2023
[j5]Tao Li
, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh:
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". IEEE Trans. Very Large Scale Integr. Syst. 31(6): 906 (2023)- [j4]Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh:
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 1078-1082 (2023) - 2022
- [j3]Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh:
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18(5): 3055-3065 (2022)
2000 – 2009
- 2006
- [j2]Ko Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura:
Domino Logic Synthesis System and its Applications. J. Circuits Syst. Comput. 15(2): 277-287 (2006) - [c4]Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa:
Budgeting-free hierarchical design method for large scale and high-performance LSIs. DAC 2006: 955-958 - 2005
- [j1]Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura:
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3351-3357 (2005) - 2004
- [c3]Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura:
Timing optimization by replacing flip-flops to latches. ASP-DAC 2004: 186-191 - [c2]Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura:
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. DAC 2004: 299-304
1990 – 1999
- 1999
- [r1]Ko Yoshikawa, Saburo Muroga:
Logic Synthesizer with Optimizations in Two Phases. The VLSI Handbook 1999 - 1991
- [c1]Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh:
Timing Optimization on Mapped Circuits. DAC 1991: 112-117
Coauthor Index
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