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Journal Articles
- 2014
[j18]Yohei Hori
, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara:
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. 22(2): 344-356 (2014)- 2013
- [j17]Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh:
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. 96-D(11): 2333-2343 (2013) - [j16]Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata:
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2533-2541 (2013) - 2012
- [j15]Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(1): 263-266 (2012) - [j14]Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue:
Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current. IEICE Trans. Electron. 95-C(6): 1089-1097 (2012) - [j13]Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki:
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 827-840 (2012) - 2011
- [j12]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
High-Performance Architecture for Concurrent Error Detection for AES Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(10): 1971-1980 (2011) - [j11]Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
An on-chip glitchy-clock generator for testing fault injection attacks. J. Cryptogr. Eng. 1(4): 265-270 (2011) - [j10]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1136-1146 (2011) - 2010
- [j9]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Profiling attack using multivariate regression analysis. IEICE Electron. Express 7(15): 1139-1144 (2010) - [j8]Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto:
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2497-2508 (2010) - [j7]Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir:
Comparative Power Analysis of Modular Exponentiation Algorithms. IEEE Trans. Computers 59(6): 795-807 (2010) - 2009
- [j6]Akashi Satoh, Takeshi Sugawara, Takafumi Aoki:
High-Performance Hardware Architectures for Galois Counter Mode. IEEE Trans. Computers 58(7): 917-930 (2009) - 2008
- [j5]Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh:
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 193-202 (2008) - 2007
- [j4]Akashi Satoh, Tadanobu Inoue:
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. Integr. 40(1): 3-10 (2007) - 2004
- [j3]Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara:
On-demand design service innovations. IBM J. Res. Dev. 48(5-6): 751-766 (2004) - [j2]Sumio Morioka, Akashi Satoh:
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 686-691 (2004) - 2003
- [j1]Akashi Satoh, Kohji Takano:
A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers 52(4): 449-460 (2003)
Conference and Workshop Papers
- 2022
- [c55]Mitsuki Terada, Akashi Satoh:
Development of Hornet Detection Camera System for Smart Beekeeping. GCCE 2022: 501-504 - [c54]Takaya Yoshitake, Akashi Satoh, Shinichiro Mito:
Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation. IEEE SENSORS 2022: 1-4 - 2019
- [c53]Kaori Uehara, Hiromichi Ikeda, Akashi Satoh:
Fertilizer Management System for A Compact Hydroponic Planter. GCCE 2019: 1018-1022 - 2018
- [c52]Akashi Satoh:
A Hydroponic Planter System to enable an Urban Agriculture Service Industry. GCCE 2018: 281-284 - 2017
- [c51]Masato Matsubayashi, Hendra Guntur, Akashi Satoh:
Security evaluation of cryptographic modules against side-channel attack using a biased data set. GCCE 2017: 1-5 - [c50]Tomohiro Nishimura, Yuji Okuyama, Ayaka Matsushita, Hiromichi Ikeda, Akashi Satoh:
A compact hardware design of a sensor module for hydroponics. GCCE 2017: 1-4 - 2016
- [c49]Makiko Kosugi, Akashi Satoh:
GPGPU software implementation of authenticated encryption algorithm Minalpher. GCCE 2016: 1-3 - [c48]Masato Matsubayashi, Akashi Satoh, Jun Ishii:
Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. GCCE 2016: 1-4 - [c47]Tomohiro Nishimura, Yuji Okuyama, Akashi Satoh:
High-accuracy and low-cost sensor module for hydroponic culture system. GCCE 2016: 1-4 - [c46]Yu Nomata, Masato Matsubayashi, Kohei Sawada, Akashi Satoh:
Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs. GCCE 2016: 1-4 - 2015
- [c45]Masato Matsubayashi, Akashi Satoh:
Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card. GCCE 2015: 565-569 - [c44]Makiko Kosug, Masahiro Yasuda, Akashi Satoh:
FPGA implementation of authenticated encryption algorithm Minalpher. GCCE 2015: 572-576 - 2014
- [c43]Hendra Guntur, Jun Ishii, Akashi Satoh:
Side-channel AttacK User Reference Architecture board SAKURA-G. GCCE 2014: 271-274 - [c42]Tatsuya Honda, Hendra Guntur, Akashi Satoh:
FPGA implementation of new standard hash function Keccak. GCCE 2014: 275-279 - 2011
- [c41]Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh:
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92 - [c40]Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh:
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig 2011: 223-228 - 2010
- [c39]Kazuyuki Kobayashi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, Leyla Nazhandali, Akashi Satoh:
Prototyping Platform for Performance Evaluation of SHA-3 Candidates. HOST 2010: 60-63 - [c38]Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Hardware Implementations of Hash Function Luffa. HOST 2010: 130-134 - [c37]Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh:
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig 2010: 298-303 - 2009
- [c36]Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh:
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES 2009: 189-204 - [c35]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Differential power analysis of AES ASIC implementations with various S-box circuits. ECCTD 2009: 395-398 - [c34]Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Development of side-channel attack standard evaluation environment. ECCTD 2009: 403-408 - [c33]Akashi Satoh, Nicolas Sklavos:
Compact and High-speed Hardware Architectures for Hash Function Tiger. ISCAS 2009: 1401-1404 - [c32]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. ISCAS 2009: 2918-2921 - [c31]Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh:
Is the differential frequency-based attack effective against random delay insertion? SiPS 2009: 051-056 - [c30]Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh:
Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. WISA 2009: 66-78 - 2008
- [c29]Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir:
Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES 2008: 15-29 - [c28]Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES 2008: 100-112 - [c27]Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda:
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL 2008: 23-28 - [c26]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Chosen-message SPA attacks against FPGA-based RSA hardware implementations. FPL 2008: 35-40 - [c25]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Systematic design of high-radix Montgomery multipliers for RSA processors. ICCD 2008: 416-421 - [c24]Akashi Satoh:
ASIC hardware implementations for 512-bit hash function Whirlpool. ISCAS 2008: 2917-2920 - [c23]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
High-performance ASIC implementations of the 128-bit block cipher CLEFIA. ISCAS 2008: 2925-2928 - [c22]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Enhanced power analysis attack using chosen message against RSA hardware implementations. ISCAS 2008: 3282-3285 - [c21]Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda:
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC 2008: 261-278 - [c20]Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig 2008: 403-408 - [c19]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. WISA 2008: 28-40 - 2007
- [c18]Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh:
DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS 2007: 1807-1810 - [c17]Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS 2007: 1847-1850 - [c16]Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS 2007: 1859-1862 - [c15]Akashi Satoh:
High-Speed Parallel Hardware Architecture for Galois Counter Mode. ISCAS 2007: 1863-1866 - [c14]Akashi Satoh, Takeshi Sugawara, Takafumi Aoki:
High-Speed Pipelined Hardware Architecture for Galois Counter Mode. ISC 2007: 118-129 - 2006
- [c13]Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh:
High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES 2006: 187-200 - [c12]Akashi Satoh:
High-speed hardware architectures for authenticated encryption mode GCM. ISCAS 2006 - 2005
- [c11]Akashi Satoh:
Hardware Architecture and Cost Estimates for Breaking SHA-1. ISC 2005: 259-273 - [c10]Akashi Satoh, Tadanobu Inoue:
ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. ITCC (1) 2005: 532-537 - 2003
- [c9]Akashi Satoh, Sumio Morioka:
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES 2003: 304-318 - [c8]Akashi Satoh, Sumio Morioka:
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC 2003: 252-266 - 2002
- [c7]Sumio Morioka, Akashi Satoh:
An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002: 172-186 - [c6]Sumio Morioka, Akashi Satoh:
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD 2002: 98-103 - [c5]Akashi Satoh, Sumio Morioka:
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC 2002: 48-62 - 2001
- [c4]Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh:
A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254 - 2000
- [c3]Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon:
High-Speed MARS Hardware. AES Candidate Conference 2000: 305-316 - 1997
- [c2]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285 - [c1]Akashi Satoh, Yoshinao Kobayashi, Hideto Niijima, Nobuyuki Ooba, Seiji Munetoh, Sadamichi Sone:
A High-Speed Small RSA Encryption LSI with Low Power Dissipation. ISW 1997: 174-187
Coauthor Index
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