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ORCIDJing-Hong Conan Zhan
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2020 – today
- 2020
[c16]Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a
:
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS. ISSCC 2020: 178-180
2010 – 2019
- 2019
- [c15]Chih-Ming Hung, Alex T. C. Lin, B. C. Peng, Hua Wang, Jui-Lin Hsu, Yen-Ju Lu, Wei-Show Hsu, Jing-Hong Conan Zhan, Brian Juan, Chi-Hang Lok, Sam Lee, P. C. Hsiao, Qiang Zhou, Mark Wei, Hsiang-Yun Chu, Yu-Lun Chen, Chao-Ching Hung, Kevin Fong, Po-Chun Huang, Pierce Chen, Sheng-Yuan Su, Yan-Jiun Chen, Kehou Chen, Chun-Chao Tung, Yi-Jhan Hsieh, Tzung-Chuen Tsai, Yi-Fu Chen, Wei-Kuo Hsin, Liang Guo, Hanfei Liu, Dapeng Jin:
Toward Automotive Surround-View Radars. ISSCC 2019: 162-164 - 2014
- [c14]YuLi Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai, Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan:
28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. ISSCC 2014: 472-473 - 2013
- [c13]Marc Tiebout, Jing-Hong Conan Zhan:
Session 20 overview: Frequency generation. ISSCC 2013: 344-345 - 2012
- [c12]Yuan-Hung Chung, Min Chen, Wei-Kai Hong, Jie-Wei Lai, Sheng-Jau Wong, Chien-Wei Kuan, Hong-Lin Chu, Chihun Lee, Chih-Fan Liao, Hsuan-Yu Liu, Hong-Kai Hsu, Li-Chun Ko, Kuo-Hao Chen, Chao-Hsin Lu, Tsung-Ming Chen, YuLi Hsueh, Chunwei Chang, Yi-Hsien Cho, Chih-Hsien Shen, Yuan Sun, Eng-Chuan Low, Xudong Jiang, Deyong Hu, Weimin Shu, Jhy-Rong Chen, Jui-Lin Hsu, Chia-Jui Hsu, Jing-Hong Conan Zhan, Osama Shana'a, Guang-Kaai Dehng, George Chien:
A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS. ISSCC 2012: 172-174 - 2011
- [j6]Alberto Valdes-Garcia, Scott K. Reynolds, Arun Natarajan, Dong Gun Kam, Duixian Liu, Jie-Wei Lai, Yen-Lin Oscar Huang, Ping-Yu Chen, Ming-Da Tsai, Jing-Hong Conan Zhan, Sean Nicolson, Brian A. Floyd:
Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications. IEEE Commun. Mag. 49(4): 120-131 (2011) - [j5]Arun Natarajan, Scott K. Reynolds, Ming-Da Tsai, Sean T. Nicolson, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Yen-Lin Oscar Huang, Alberto Valdes-Garcia, Brian A. Floyd:
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 46(5): 1059-1075 (2011) - [c11]Jerry Lin, Franz Dielacher, Jing-Hong Conan Zhan, Robert Payne:
Good, bad, ugly - 20 years of broadband evolution: What's next? ISSCC 2011: 525 - 2010
- [j4]Alberto Valdes-Garcia, Sean T. Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Brian A. Floyd:
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 45(12): 2757-2773 (2010) - [c10]Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd:
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications. ISSCC 2010: 218-219
2000 – 2009
- 2009
- [j3]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang:
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. IEEE J. Solid State Circuits 44(8): 2182-2192 (2009) - 2008
- [j2]Jing-Hong Conan Zhan, Brent R. Carlton, Stewart S. Taylor:
A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS. IEEE J. Solid State Circuits 43(5): 1132-1137 (2008) - [c9]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh:
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. CICC 2008: 749-752 - [c8]Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan:
A fractional spur reduction technique for RF TDC-based all digital PLLs. ESSCIRC 2008: 422-425 - [c7]Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh:
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. ISSCC 2008: 200-201 - 2007
- [c6]Bevin G. Perumana, Jing-Hong Conan Zhan, Stewart S. Taylor, Joy Laskar:
A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS. ESSCIRC 2007: 372-375 - 2006
- [c5]Jing-Hong Conan Zhan, Stewart S. Taylor:
A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications. ISSCC 2006: 721-730 - 2005
- [c4]Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay:
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-fT SiGe process. CICC 2005: 552-555 - [c3]Brian Welch, Jing-Hong Conan Zhan, Kevin T. Kornegay:
A family of SiGe quadrature oscillators for microwave applications. ISCAS (5) 2005: 4891-4894 - 2004
- [j1]Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay:
A 25-GHz emitter degenerated LC VCO. IEEE J. Solid State Circuits 39(11): 2062-2064 (2004) - [c2]Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay:
A comparative study of MOS VCOs for low voltage high performance operation. ISLPED 2004: 244-247 - 2003
- [c1]Jing-Hong Conan Zhan, Kyle Maurice, Jon S. Duster, Kevin T. Kornegay:
Analysis of emitter degenerated LC oscillators using bipolar technologies. ISCAS (1) 2003: 669-672
Coauthor Index
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