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2020 – today
- 2024
[j6]Yu-Guang Chen
, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann:
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1580-1593 (2024)- [c32]Yu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin:
GNN-Based INC and IVC Co-Optimization for Aging Mitigation. ETS 2024: 1-4 - [c31]Yu-Guang Chen, Tzong-Ying Lee, Yi-Ting Lin:
Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects. ISCAS 2024: 1-5 - [c30]Yu-Guang Chen, Zhi-Wei Liu, Ying-Jing Tsai:
Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference. ISVLSI 2024: 112-117 - 2023
- [j5]Wei-Tse Hung, Yu-Guang Chen, Jhen-Gang Lin, Yun-Wei Yang, Cheng-Hong Tsai, Mango Chia-Tso Chao:
DRC Violation Prediction After Global Route Through Convolutional Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1425-1438 (2023) - [c29]Yin-Rong Zhuo, Hui-Lin Chen, Yu-Guang Chen:
DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs. APSIPA ASC 2023: 1392-1397 - [c28]Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. ASP-DAC 2023: 13-18 - [c27]Yu-Guang Chen, Ying-Jing Tsai:
Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. DFT 2023: 1-6 - [c26]Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu, Mango Chia-Tso Chao:
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. ACM Great Lakes Symposium on VLSI 2023: 313-319 - [c25]Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang:
Invited Paper: Overview of 2023 CAD Contest at ICCAD. ICCAD 2023: 1-6 - 2022
- [c24]Yu-Guang Chen, Tsung-Han Hsieh, Yi-Chen Ho, Jing-Yang Jou:
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design. AICAS 2022: 250-253 - [c23]Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato:
Overview of 2022 CAD Contest at ICCAD. ICCAD 2022: 92:1-92:3 - [c22]Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin:
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. ISOCC 2022: 161-162 - 2021
- [j4]Yu-Guang Chen, Ing-Chao Lin, Kun-Wei Chiu, Cheng-Hsuan Liu:
An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation. Integr. 80: 60-71 (2021) - [c21]Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. DFT 2021: 1-4 - [c20]Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato:
Overview of 2021 CAD Contest at ICCAD. ICCAD 2021: 1-3 - [c19]Yu-Guang Chen, Hung-Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou:
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. ISOCC 2021: 290-291 - [c18]Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei:
A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning. ISQED 2021: 476-481 - [c17]Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou:
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. SoCC 2021: 278-283 - 2020
- [c16]Wen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, Mango C.-T. Chao:
Power Distribution Network Generation for Optimizing IR-Drop Aware Timing. ICCAD 2020: 146:1-146:9 - [c15]Yu-Guang Chen:
An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling. ICCE-TW 2020: 1-2 - [c14]Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen:
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience. ISPD 2020: 95-102 - [c13]Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin:
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems. ISQED 2020: 117-122
2010 – 2019
- 2019
- [c12]Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke:
ROAD: Improving Reliability of Multi-core System via Asymmetric Aging. ICCAD 2019: 1-8 - [c11]Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu:
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI 2019: 218-223 - 2018
- [c10]Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin:
An efficient NBTI-aware wake-up strategy for power-gated designs. DATE 2018: 901-904 - 2017
- [c9]Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang:
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC 2017: 543-548 - 2016
- [c8]Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang:
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization. ASP-DAC 2016: 250-255 - 2015
- [j3]Yu-Guang Chen, Wan-Yu Wen, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 577-588 (2015) - [c7]Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang:
Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. ISPD 2015: 41-48 - 2014
- [j2]Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, Shih-Chieh Chang:
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 507-518 (2014) - [c6]Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-Yu Wen, Yiyu Shi, Shih-Chieh Chang:
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs. DAC 2014: 98:1-98:6 - [c5]Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. DATE 2014: 1-4 - 2012
- [c4]Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Hui Geng, Shih-Chieh Chang:
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. ICCAD 2012: 309-316 - [c3]Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang:
Efficient on-line module-level wake-up scheduling for high performance multi-module designs. ISPD 2012: 97-104 - 2011
- [c2]Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang:
NBTI-aware power gating design. ASP-DAC 2011: 609-614 - 2010
- [j1]Shuxi Liu, Ming-Yu Wang, Yu-Guang Chen, Shan Li:
A novel fuzzy direct torque control system for three-level inverter-fed induction machine. Int. J. Autom. Comput. 7(1): 78-85 (2010)
2000 – 2009
- 2006
- [c1]Chun-Hsin Wang, Chang-Wu Yu, Chiu-Kuo Liang, Kun-Ming Yu, Wen Ouyang, Ching-Hsien Hsu, Yu-Guang Chen:
Tracers placement for IP traceback against DDoS attacks. IWCMC 2006: 355-360
Coauthor Index
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