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ORCIDMayukh Bhattacharya
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Books and Theses
- 1999
[b1]Mayukh Bhattacharya:
Simulation and emulation of digital integrated circuits containing resonant tunneling diodes. University of Michigan, USA, 1999
Journal Articles
- 2024
- [j6]Jayeeta Chaudhuri
, Mayukh Bhattacharya, Krishnendu Chakrabarty:
DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2930-2943 (2024) - 2020
- [j5]Sayandeep Sanyal, Mayukh Bhattacharya, Amit Patra, Pallab Dasgupta:
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits. J. Electron. Test. 36(6): 719-730 (2020) - 2001
- [j4]Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits 36(6): 924-932 (2001) - [j3]Mayukh Bhattacharya, Pinaki Mazumder:
Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 39-50 (2001) - [j2]Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta:
A physical design tool for built-in self-repairable RAMs. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 352-364 (2001) - 1998
- [j1]Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Jian Ping Sun, George I. Haddad:
Digital circuit applications of resonant tunneling devices. Proc. IEEE 86(4): 664-686 (1998)
Conference and Workshop Papers
- 2023
- [c15]Sayandeep Sanyal, Mayukh Bhattacharya, Pallab Dasgupta, Amit Patra:
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection. VLSID 2023: 325-330 - 2022
- [c14]Jonti Talukdar, Arjun Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty:
Automatic Structural Test Generation for Analog Circuits using Neural Twins. ITC 2022: 145-154 - [c13]Mayukh Bhattacharya, Beatrice Solignac, Michael Dürr:
Application of Sampling in Industrial Analog Defect Simulation. ITC 2022: 436-445 - 2019
- [c12]Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya:
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. ATS 2019: 135-140 - [c11]Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya:
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis. ACM Great Lakes Symposium on VLSI 2019: 123-128 - 2018
- [c10]Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti:
Innovative practices on functional testing and fault simulation for FuSa. VTS 2018: 1 - 2001
- [c9]Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González, Pinaki Mazumder:
A 250-MHz, 32-bit quantum MOS correlator prototype. ICECS 2001: 1501-1504 - [c8]Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya:
Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. VLSI Design 2001: 327-332 - [c7]Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax:
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. VLSI Design 2001: 470-474 - 2000
- [c6]Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder:
A prototyping technique for large-scale RTD-CMOS circuits. ISCAS 2000: 635-638 - [c5]Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. ISMVL 2000: 323-330 - [c4]Mayukh Bhattacharya, Pinaki Mazumder:
Convergence Issues in Resonant Tunneling Diode Circuit Simulation. VLSI Design 2000: 499- - 1999
- [c3]Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
A Physical Design Tool for Built-in Self-Repairable Static RAMs. DATE 1999: 714- - 1998
- [c2]Mayukh Bhattacharya, Pinaki Mazumder:
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. Great Lakes Symposium on VLSI 1998: 65-70 - [c1]Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González:
Circuit Design using Resonant Tunneling Diodes. VLSI Design 1998: 501-506
Coauthor Index
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