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ORCID36th VLSI Design 2023: Hyderabad, India
- 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023. IEEE 2023, ISBN 979-8-3503-4678-7
- Eric Homan, Codey Mathis, Chonghan Lee, Harland M. Patch, Christina M. Grozinger, Vijay Narayanan:
InsectEye: An Intelligent Trap for Insect Biodiversity Monitoring. 1-6 - Meghvern Pathak, Rahul Shrestha:
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. 1-6 - Sujata Kotabagi, Raghavendra Nayak, Sachin Dalabanjan, Vineet P. N, Priyanka L. Patil, Sameer Hemadri:
Maximum Power Point Tracking using Buck-Boost converter for EH-PMIC. 1-6 - Sumanta Pyne:
Translation of Array Expressions for in-Memory Computation on Memristive Crossbar. 1-6 - Vibhu
, Sparsh Mittal, Vivek Kumar:
Machine Learning-based model for Single Event Upset Current Prediction in 14nm FinFETs. 1-6 - K. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi:
Design of Energy Efficient and Low Delay Posit Multiplier. 1-6 - Sumana Ghosh:
Delay-Aware Control for Autonomous Systems. 1-6 - Somnath Mondal, Sachin Patkar, T. K. Pal:
Hardware implementation of Ring-LWE lattice cryptography with BCH and Gray coding based error correction. 1-6 - Rakesh M. B., Pabitra Das, Sai Pranav K. R, Amit Acharyya:
GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL Designs. 1-6 - Sira Rao, Baskaran Chidambaram, Prasanth V., Karthik Rajakumar, Pramod Prabhakara, Praveen Ravichandran, Shailesh Ghotgalkar, Ashish Vanjari, Mihir Mody:
Live & Seamless Firmware Upgrade in Real Time Control Systems. 1-5 - Sowmyashree S, Hitesh Shrimali:
A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR. 1-6 - Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi:
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. 1-6 - Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta:
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. 1-6 - N. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor:
WIB-SAR: Write Intensity Based Selective Address Remapping. 1-6 - Sivalingam Thirubalan, Suresh Kumar Kopparti, Desmond Tan Hai Peng:
Efficient 3D Modeling Methodology for High-Speed Channels. 1-6 - Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena:
A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications. 1-5 - Apurba Prasad Padhy, Bishnu Prasad Das:
Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application. 7-12 - Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani:
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. 25-30 - Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese:
Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. 42-47 - Gaurav Saraswat, Anuj Parashar:
Voltage Boosted Schmitt Trigger Sense Amplifier (VBSTSA) With Improved Offset And Reaction Time For High Speed SRAMs. 48-52 - Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta:
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. 59-62 - Sanjoy Kumar Dey, Mukul Sarkar, Shouribrata Chatterjee:
A low-power resistive tail dynamic comparator with self-shut mechanism. 63-68 - Debjit Batabyal, Sandeep Kumar Singh, Rajnish Kumar Mishra, Anuj Grover:
A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced Currents. 69-74 - Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi:
Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC. 75-80 - Siva Charan Nimmagadda, Hari Bilash Dubey:
Programmable Delay Line With Inherent Duty Cycle Correction. 81-86 - Aditya Ramkumar, Anshul Verma, Bishnu Prasad Das:
Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases. 92-97 - Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin Leng Sun Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey:
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. 98-103 - Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. 104-108 - Swetha Ananthanarayanan, Bhupendra Singh Reniwal, Abhishek Upadhyay:
Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach. 109-114 - Belal Iqbal, Anuj Grover, Harsh Rawat:
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology. 121-126 - Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal:
Supply Noise and Peak Current Reduction in High-Speed Output Drivers. 127-132 - Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal:
An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. 133-138 - Nandit Kaushik, B. Srinivasu:
Memristor-based High Speed and Area Efficient Comparators in IMPLY Logic. 139-144 - Vishwajeet S. B, Vaibhavi Solanki, Anand D. Darji:
Design of Hardware Efficient Approximate DCT Architecture. 145-150 - Krishnan Sukumar, Santosh Vodnala, Ravindra Ayyagari, Animesh Jain, Thanapandi Ganesan, Rajesh R:
Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes. 157-162 - Vinay Kumar, Vijay Sahu, Ambar Khanda, Sudhir Kumar:
Dynamic Keeper for 1R1W 8T-SRAM to Enable Read Operation at 150c till 0.5v in 5nm FinFET. 163-168 - Padmaja Bhamidipati, Ranga Vemuri:
ASPIRE: An Intermediate Representation for Abstract Security Policies. 175-180 - Santanu Kundu, Chetan Suryakant Padharia, Ravi Sankar Kerla:
MLTDRC: Machine Learning Driven Faster Timing Design Rule Check Convergence. 181-186 - Masataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama:
Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. 193-198 - Biswojit Nayak, B. N. Bhramar Ray:
ISP: An Improved Slicing Pair Code for Skewed Slicing Floorplan. 205-210 - Darakshan Jamal, Ratheesh T. Veetil:
Efficient MBIST Area and Test Time Estimator Using Machine Learning Technique. 223-228 - Kahkeshan Naz, Rohit Jindal, Sai Boothkuri:
A Novel AI Based Approach for Performance validation. 229-233 - Hanumantharaya H, Ratheesh T. Veetil, Anvesh Gadi:
Signal Agnostic Scalable Scan Wrapper Design. 234-239 - Suriya Srinivasan, Ranga Vemuri:
Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. 240-245 - Samuel Abrams, Vijaykrishnan Narayanan:
Extending Action Recognition in the Compressed Domain. 246-251 - Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut:
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. 252-257 - Kailash Prasad, Ayush Srivastava, Nistha Baruah, Joycee Mekie:
Fast and Robust Sense Amplifier for Digital In Memory Computing. 258-263 - Noble G, Nalesh S, S. Kala:
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. 264-269 - Anamika Sharma, Sachin Divekar, Rajesh Zele:
A Portable Ultra-low-cost Multi-Gas Sensing System-on-Module for Wireless Air Quality Monitoring Network. 270-273 - Shyam Peraka, SK Irfan Ali, Durga Vasu Mogili, Ashok Kumar Palivela, Sudheer Reddy, Jyotsna Bavisetti, Dhanush Reddy Y:
FPGA based Smart and Sustainable Agriculture. 274-278 - Abhishek Jadhav, Varsha Bhide, T. N. V. Raghuram, Tapas Nandy:
SV Based Fast & Accurate Verification Methodology for CTLE Adaptation Algorithm. 279-283 - Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala:
A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET. 284-289 - Reshma Sinha, Jasdeep Kaur:
Enhanced Performance Parameters of Magnetic Tunnel Junction with Composite Dielectric Barrier. 290-294 - Thomas Grurl, Christoph Pichler, Jürgen Fuß, Robert Wille:
Automatic Implementation and Evaluation of Error-Correcting Codes for Quantum Computing: An Open-Source Framework for Quantum Error Correction. 301-306 - Amina Haroon, Ram Krishna Ghosh, Sneh Saurabh:
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis. 307-312 - Swati Shilaskar, Anup Behare, Ketki Sonawane, Shripad Bhatlawande:
Post Silicon Validation for I2C (SMBUS) Peripheral. 313-318 - M. Mohamed Asan Basiri, PVSR Bharadwaja:
Efficient FPGA Implementations of Lifting based DWT using Partial Reconfiguration. 319-324 - Sayandeep Sanyal, Mayukh Bhattacharya, Pallab Dasgupta, Amit Patra:
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection. 325-330 - Omkareshwar Gundoji, Dighanchal Banerjee, Sounak Dey, Arpan Pal:
Mutual Information based Efficient Spike Encoding on FPGA. 331-336 - Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran:
SANNA: Secure Acceleration of Neural Network Applications. 337-342 - Sunny Bezawada, Battu Prakash Reddy:
The Acceleration of OPUS Codec Using Processor - FPGA Co-processing. 343-347 - Shivam Nigam, Mukund Murali, Hari Shanker Gupta, Saurabh Saxena:
A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS. 348-352 - Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Evaluating the Impact of Transition Delay Faults in GPUs. 353-358 - Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. 359-364 - Vaishnavi Sankar, Balachander Sathianarayanan, Nirmala Devi Manickam, M. Jayakumar:
Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique. 365-370 - Vishesh Mishra, Neelofar Hassan, Akshay Mehta, Urbi Chatterjee:
DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders. 371-376 - Alisha P. B, Tripti S. Warrier:
True Random Number Generator based on Voltage-Gated Spintronic structure. 377-382 - Shyam Peraka, SK Irfan Ali, Reddy Sudheer, Pilli Praveen Kumar, Goutham Kondala, Dimple Samal:
A Novel Approach for Assisting Blind People Using a Smart Wearable Device. 383-388 - Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. 389-394 - Harikrishna Kambham, Srayan Sankar Chatterjee, Adithya Sunil Edakkadan, Abhishek Srivastava:
Analysis and Design of Low Phase Noise 20 GHz VCO for Frequency Modulated Continuous Wave Chirp Synthesizers in mmWave Radars. 395-400 - Sresthavadhani Mantha, Adithya Sunil Edakkadan, Arpit Sahni, Abhishek Srivastava:
An mmWave Frequency Range Multi-Modulus Programmable Divider for FMCW Radar Applications. 407-412
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last updated on 2025-05-06 21:40 CEST by the dblp team
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