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ORCIDSergei Devadze
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2020 – today
- 2024
[c36]Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab:
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS 2024: 1-2- 2023
- [c35]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT 2023: 1-6 - [i2]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR abs/2308.15917 (2023) - 2022
- [i1]Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman:
HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR abs/2212.04374 (2022)
2010 – 2019
- 2019
- [c34]Lembit Jürimägi
, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran:
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS 2019: 299-304 - 2018
- [c33]Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik:
Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES 2018: 305-310 - [c32]Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin:
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS 2018: 1-6 - 2017
- [j8]Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken:
Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. IEEE Des. Test 34(6): 27-35 (2017) - [j7]Igor Aleksejev, Artur Jutman, Sergei Devadze:
Run-time reconfigurable instruments for advanced board-level testing. IEEE Instrum. Meas. Mag. 20(4): 23-30 (2017) - [c31]Sergei Odintsov, Artur Jutman, Sergei Devadze:
Marginal PCB assembly defect detection on DDR3/4 memory bus. ITC 2017: 1-10 - 2016
- [j6]Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin:
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. J. Electron. Test. 32(3): 245-255 (2016) - [c30]Artur Jutman, Igor Aleksejev, Sergei Devadze:
On coverage of timing related faults at board level. ETS 2016: 1-2 - [c29]Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao:
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL 2016: 1-8 - [c28]Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath:
A suite of IEEE 1687 benchmark networks. ITC 2016: 1-10 - [c27]Konstantin Shibin, Sergei Devadze, Artur Jutman:
On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. LATS 2016: 69-74 - 2015
- [j5]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems 39(8): 909-918 (2015) - [j4]Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik:
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems 39(8): 1130-1138 (2015) - [c26]Maksim Gorev, Raimund Ubar, Sergei Devadze:
Fault simulation with parallel exact critical path tracing in multiple core environment. DATE 2015: 1180-1185 - [c25]Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze:
Combinational fault simulation in sequential circuits. ISCAS 2015: 2876-2879 - [c24]Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin:
Virtual reconfigurable scan-chains on FPGAs for optimized board test. LATS 2015: 1-6 - 2014
- [c23]Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath:
Design, Verification, and Application of IEEE 1687. ATS 2014: 93-100 - [c22]Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik:
Critical Path Tracing Based Simulation of Transition Delay Faults. DSD 2014: 108-113 - [c21]Konstantin Shibin, Sergei Devadze, Artur Jutman:
Asynchronous Fault Detection in IEEE P1687 Instrument Network. NATW 2014: 73-78 - 2013
- [j3]Artur Jutman, Sergei Devadze, Konstantin Shibin:
Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Des. Test 30(5): 26-35 (2013) - [c20]Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski:
On in-system programming of non-volatile memories. MIXDES 2013: 408-413 - [c19]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP 2013: 1-6 - 2012
- [c18]Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel:
Embedded synthetic instruments for Board-Level testing. ETS 2012: 1 - [c17]Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel:
FPGA-based synthetic instrumentation for board test. ITC 2012: 1-10 - 2011
- [j2]Eero Ivask, Sergei Devadze, Raimund Ubar:
Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. 12(1) (2011) - [c16]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze:
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538 - [c15]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze:
SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582 - [c14]Artur Jutman, Sergei Devadze, Igor Aleksejev:
Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC 2011: 1-4 - 2010
- [c13]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884 - [c12]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19 - [c11]Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663 - [c10]Anton Tsertov, Artur Jutman, Sergei Devadze:
Testing beyond the SoCs in a lego style. EWDTS 2010: 334-338 - [c9]Eero Ivask, Sergei Devadze, Raimund Ubar:
Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC 2010: 67-76 - [c8]Eero Ivask, Sergei Devadze, Raimund Ubar:
Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS 2010: 145-152
2000 – 2009
- 2009
- [c7]Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar:
Fast extended test access via JTAG and FPGAs. ITC 2009: 1-7 - [c6]Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar:
Turning JTAG inside out for fast extended test access. LATW 2009: 1-6 - 2008
- [c5]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672 - [c4]Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee:
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227 - 2007
- [j1]Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke:
Learning Digital Test and Diagnostics via Internet. Int. J. Online Eng. 3(1) (2007) - [c3]Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS 2007: 131-136 - 2006
- [c2]Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar:
Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW 2006: 97-102 - 2005
- [c1]Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman:
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
Coauthor Index
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