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ORCIDHaridimos T. Vergos
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- affiliation: University of Patras, Greece
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2010 – 2019
- 2016
[c43]George Blanas, Haridimos T. Vergos:
Extending the viability of power signature - Based IP watermarking in the SoC era. ICECS 2016: 281-284- 2015
- [j25]Haridimos T. Vergos, Dimitris Bakalis
, A. Anastasiou:
Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst. Signal Process. 34(4): 1041-1056 (2015) - 2014
- [c42]Anastasios N. Bikos, Haridimos T. Vergos:
Easily verified IP watermarking. DTIS 2014: 1-2 - 2013
- [c41]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Reverse converters for RNSs with diminished-one encoded channels. EUROCON 2013: 1798-1805 - [c40]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
RNS assisted image filtering and edge detection. DSP 2013: 1-6 - [c39]Alexios Thanos, Haridimos T. Vergos:
Fast parallel-prefix Ling-carry adders in QCA nanotechnology. ICECS 2013: 565-568 - 2012
- [j24]Haridimos T. Vergos:
Area-time efficient end-around inverted carry adders. Integr. 45(4): 388-394 (2012) - [j23]Haridimos T. Vergos, Dimitris Bakalis:
Area-time efficient multi-modulus adders and their applications. Microprocess. Microsystems 36(5): 409-419 (2012) - [j22]Haridimos T. Vergos, Giorgos Dimitrakopoulos:
On Modulo 2^n+1 Adder Design. IEEE Trans. Computers 61(2): 173-186 (2012) - [c38]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Residue-to-Binary Converters Design. DSD 2012: 65-72 - 2011
- [j21]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. Circuits Syst. Signal Process. 30(6): 1445-1461 (2011) - [j20]Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou:
Efficient modulo 2n±1 squarers. Integr. 44(3): 163-174 (2011) - [c37]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. DSD 2011: 468-475 - [c36]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
On the use of double-LSB and signed-LSB encodings for RNS. DSP 2011: 1-6 - 2010
- [j19]Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Fast modulo 2n+1 multi-operand adders and residue generators. Integr. 43(1): 42-48 (2010) - [j18]Haridimos T. Vergos, Dimitris Bakalis:
On Implementing Efficient Modulo 2n + 1 Arithmetic Components. J. Circuits Syst. Comput. 19(5): 911-930 (2010) - [c35]Dimitris Bakalis, Haridimos T. Vergos:
Area-Efficient Multi-moduli Squarers for RNS. DSD 2010: 408-411 - [c34]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Forward and Reverse Converters. ISVLSI 2010: 11-16 - [c33]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Forward and Reverse Converters. ISVLSI (Selected papers) 2010: 231-244 - [c32]Haridimos T. Vergos:
A Family of Area-Time Efficient Modulo 2n+1 Adders. ISVLSI 2010: 442-443
2000 – 2009
- 2009
- [j17]Haridimos T. Vergos, Costas Efstathiou:
Efficient modulo 2n+1 adder architectures. Integr. 42(2): 149-157 (2009) - [c31]Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos:
Efficient architectures for modulo 2n-1 squares. DPS 2009: 1-6 - [c30]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Novel modulo 2n+1 subtractors. DPS 2009: 1-5 - 2008
- [j16]Haridimos T. Vergos, Costas Efstathiou:
A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1041-1045 (2008) - [c29]Haridimos T. Vergos, Dimitris Bakalis:
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD 2008: 752-759 - [c28]Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Efficient modulo 2n + 1 multi-operand adders. ICECS 2008: 694-697 - 2007
- [j15]D. Adamidis, Haridimos T. Vergos:
RNS multiplication/sum-of-squares units. IET Comput. Digit. Tech. 1(1): 38-48 (2007) - [j14]Haridimos T. Vergos, Costas Efstathiou:
Design of efficient modulo 2n+1 multipliers. IET Comput. Digit. Tech. 1(1): 49-57 (2007) - [c27]Haridimos T. Vergos:
An Efficient BIST Scheme for Non-Restoring Array Dividers. DSD 2007: 664-667 - 2006
- [j13]Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52(1): 1-12 (2006) - [c26]Haridimos T. Vergos, Costas Efstathiou:
Novel Modulo 2n + 1 Multipliers. DSD 2006: 168-175 - 2005
- [j12]Haridimos T. Vergos, Costas Efstathiou:
On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. 14(5): 965-972 (2005) - [j11]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005) - [c25]D. Adamidis, Haridimos T. Vergos:
Modulo 2n - 1 multiplication/sum-of-squares units. ECCTD 2005: 143-146 - [c24]Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - [c23]Nikolaos Kostaras, Haridimos T. Vergos:
KoVer: A Sophisticated Residue Arithmetic Core Generator. IEEE International Workshop on Rapid System Prototyping 2005: 261-263 - 2004
- [j10]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004) - [j9]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004) - [c22]Haridimos T. Vergos, Costas Efstathiou:
Diminished-1 Modulo 2n + 1 Squarer Design. DSD 2004: 380-386 - 2003
- [j8]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003) - [j7]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003) - [c21]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336 - [c20]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos:
Efficient modulo 2n+1 tree multipliers for diminished-1 operands. ICECS 2003: 200-203 - [c19]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c18]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. ISCAS (5) 2003: 225-228 - [c17]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - 2002
- [j6]Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou:
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. 48(4-5): 125-135 (2002) - [j5]Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002) - [c16]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Ling adders in CMOS standard cell technologies. ICECS 2002: 485-488 - 2001
- [j4]Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou:
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 12(3): 431-448 (2001) - [c15]Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217 - [c14]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
On the design of modulo 2n±1 adders. ICECS 2001: 517-520 - [c13]Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED 2001: 350-355 - [c12]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247 - 2000
- [j3]Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000) - [c11]Costas Efstathiou, Haridimos T. Vergos:
Modified Booth 1's complement and modulo 2n-1 multipliers. ICECS 2000: 637-640 - [c10]Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos:
Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED 2000: 433-438
1990 – 1999
- 1999
- [j2]Dimitris Nikolos, Haridimos T. Vergos:
On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers 48(10): 1138-1144 (1999) - [c9]G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos:
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium 1999: 47-52 - [c8]Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas:
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116 - [c7]Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT 1999: 121-129 - [c6]Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC 1999: 267-282 - [c5]Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23 - [c4]Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos:
Path delay fault testing of Benes multistage interconnection networks. ICECS 1999: 1097-1100 - [c3]C. Ninos, Haridimos T. Vergos, Dimitris Nikolos:
Design and Analysis of On-Chip CPU Pipelined Caches. VLSI 1999: 161-172 - 1996
- [c2]Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris:
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. DFT 1996: 53-58 - [c1]Dimitris Nikolos, Haridimos T. Vergos:
On the Yield of VLSI Processors with on-chip CPU Cache. EDCC 1996: 214-230 - 1995
- [j1]Haridimos T. Vergos, Dimitris Nikolos:
Efficient fault tolerant cache memory design. Microprocess. Microprogramming 41(2): 153-169 (1995)
Coauthor Index
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