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ORCIDHao Zheng 0001
Person information
- affiliation: University of South Florida, Tampa, FL, USA
- affiliation: University of Utah, Salt Lake City, UT, USA
Other persons with the same name
- Hao Zheng — disambiguation page
- Hao Zheng 0002 — Georgia Institute of Technology, Atlanta, GA, USA
- Hao Zheng 0003 — Google (and 1 more)
- Hao Zheng 0004
![[0000-0001-8381-0049]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8381-0049")
— Xi'an Jiaotong University, School of Electronics and Information Engineering, China - Hao Zheng 0005 — University of Central Florida, Department of Electrical and Computer Engineering, Orlando, FL, USA (and 1 more)
- Hao Zheng 0006 — University of Louisiana at Lafayette, LA, USA (and 2 more)
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Journal Articles
- 2024
[j11]Md Rubel Ahmed, Bardia Nadimi, Hao Zheng:
AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2191-2204 (2024)- 2022
- [j10]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Patterns From Concurrent Execution Traces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2758-2762 (2022) - 2016
- [j9]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers:
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. 118: 24-39 (2016) - 2015
- [j8]Hao Zheng, Zhen Zhang, Chris J. Myers, Emmanuel Rodriguez, Yingying Zhang:
Compositional Model Checking of Concurrent Systems. IEEE Trans. Computers 64(6): 1607-1621 (2015) - 2014
- [j7]Hao Zheng, Yingying Zhang:
Local State Space Analysis Leads to Better Partial Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 839-852 (2014) - 2010
- [j6]Hao Zheng, Haiqiong Yao, Tomohiro Yoneda:
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. IEEE Trans. Computers 59(4): 561-573 (2010) - 2009
- [j5]Haiqiong Yao, Hao Zheng:
Automated Interface Refinement for Compositional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 433-446 (2009) - 2008
- [j4]Hao Zheng, Jared Ahrens, Tian Xia:
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1343-1347 (2008) - 2007
- [j3]Tian Xia, Hao Zheng:
Timing Jitter Characterization for Mixed-Signal Production Test Using the Interpolation Algorithm. IEEE Trans. Ind. Electron. 54(2): 1014-1023 (2007) - 2006
- [j2]Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda:
Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 403-412 (2006) - 2003
- [j1]Hao Zheng, Eric Mercer, Chris J. Myers:
Modular verification of timed circuits using automatic abstraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1138-1153 (2003)
Conference and Workshop Papers
- 2024
- [c33]Mohammad Ahmadi, Lukas Buecherl, Chris J. Myers, Zhen Zhang, Chris Winstead, Hao Zheng:
Rare-Event Guided Analysis of Infinite-State Chemical Reaction Networks. QEST+FORMATS 2024: 196-212 - 2023
- [c32]Md Rubel Ahmed, Bardia Nadimi, Hao Zheng:
System-on-Chip Message Flow Mining with Masked-Language Models. MWSCAS 2023: 496-500 - [c31]Joshua Jeppson, Matthias Volk, Bryant Israelsen, Riley Roberts, Andrew Williams, Lukas Buecherl, Chris J. Myers, Hao Zheng, Chris Winstead, Zhen Zhang:
STAMINA in C++: Modernizing an Infinite-State Probabilistic Model Checker. QEST 2023: 101-109 - 2021
- [c30]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System Designs. ICCD 2021: 492-499 - [c29]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. ISQED 2021: 374-380 - [c28]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
A Comparative Study of Specification Mining Methods for SoC Communication Traces. ISVLSI 2021: 31-36 - 2020
- [c27]Hernan M. Palombo, Egor Dolzhenko, Jay Ligatti, Hao Zheng:
Stream-Monitoring Automata. ICSCA 2020: 313-320 - [c26]Lakshmi Kavya Kalyanam, Vishalini Laguduva Ramnath, Srinivas Katkoori, Hao Zheng:
A Distributed Framework for Real Time Object Detection at Low Frame Rates with IoT Edge Nodes. iSES 2020: 285-290 - [c25]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. ISQED 2020: 389-394 - 2019
- [c24]Thakur Neupane, Chris J. Myers, Curtis Madsen, Hao Zheng, Zhen Zhang:
STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis. CAV (1) 2019: 540-549 - [c23]Yuting Cao, Hao Zheng, Sandip Ray:
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug. ISQED 2019: 278-283 - 2018
- [c22]Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng:
Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors. ISVLSI 2018: 602-607 - 2017
- [c21]Hernan M. Palombo, Hao Zheng, Jay Ligatti:
POSTER: Towards Precise and Automated Verification of Security Protocols in Coq. CCS 2017: 2567-2569 - [c20]Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang:
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. ICCD 2017: 177-184 - 2016
- [c19]Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang:
Protocol-guided analysis of post-silicon traces under limited observability. ISQED 2016: 301-306 - 2014
- [c18]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers:
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS 2014: 48-62 - [c17]Hao Zheng:
Local state space construction for compositional verification of concurrent systems. SPIN 2014: 11-19 - 2012
- [c16]Hao Zheng, Andrew Price, Chris J. Myers:
Using decision diagrams to compactly represent the state space for explicit model checking. HLDVT 2012: 17-24 - [c15]Chris J. Myers, Jian Wu, Zhen Zhang, Hao Zheng, Yingying Zhang:
Poster Abstract: Methods and Tools for Verification of Cyber-Physical Systems. ICCPS 2012: 232 - [c14]Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers:
An Improvement in Partial Order Reduction Using Behavioral Analysis. ISVLSI 2012: 100-107 - [c13]Hao Zheng, Emmanuel Rodriguez, Yingying Zhang, Chris J. Myers:
A Compositional Minimization Approach for Large Asynchronous Design Verification. SPIN 2012: 62-79 - 2011
- [c12]Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers:
A Behavioral Analysis Approach for Efficient Partial Order Reduction. HASE 2011: 49-56 - 2010
- [c11]Haiqiong Yao, Hao Zheng, Chris J. Myers:
State space reductions for scalable verification of asynchronous designs. HLDVT 2010: 17-24 - [c10]Robert A. Thacker, Kevin R. Jones, Chris J. Myers, Hao Zheng:
Automatic abstraction for verification of cyber-physical systems. ICCPS 2010: 12-21 - 2009
- [c9]Hao Zheng, Haiqiong Yao, Tomohiro Yoneda:
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. ISVLSI 2009: 175-180 - 2006
- [c8]Di Mu, Tian Xia, Hao Zheng:
Data Dependent Jitter Characterization Based on Fourier Analysis. DFT 2006: 534-544 - 2005
- [c7]Tian Xia, Peilin Song, Hao Zheng:
Characterizing the VCO jitter due to the digital simultaneous switching noise. ACM Great Lakes Symposium on VLSI 2005: 70-73 - [c6]Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi:
Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. ISVLSI 2005: 218-223 - 2003
- [c5]Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda:
Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35 - 2001
- [c4]Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng:
Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340 - [c3]Hao Zheng, Eric Mercer, Chris J. Myers:
Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193 - 1999
- [c2]Brandon M. Bachman, Hao Zheng, Chris J. Myers:
Architectural Synthesis of Timed Asynchronous Systems. ICCD 1999: 354-363 - 1997
- [c1]Chris J. Myers, Hao Zheng:
An asynchronous implementation of the maxlist algorithm. ICASSP 1997: 647-650
Parts in Books or Collections
- 2019
- [p1]Thakur Neupane, Zhen Zhang, Curtis Madsen, Hao Zheng, Chris J. Myers:
Approximation Techniques for Stochastic Analysis of Biological Systems. Automated Reasoning for Systems Biology and Medicine 2019: 327-348
Informal and Other Publications
- 2024
- [i16]Bardia Nadimi, Hao Zheng:
A Multi-Expert Large Language Model Architecture for Verilog Code Generation. CoRR abs/2404.08029 (2024) - [i15]Bardia Nadimi, Hao Zheng:
Inferring Message Flows From System Communication Traces. CoRR abs/2405.12426 (2024) - 2023
- [i14]Md Rubel Ahmed, Bardia Nadimi, Hao Zheng:
AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs. CoRR abs/2308.03523 (2023) - 2022
- [i13]Md Rubel Ahmed, Hao Zheng:
Deep Bidirectional Transformers for SoC Flow Specification Mining. CoRR abs/2203.13182 (2022) - [i12]Mohammad Ahmadi, Zhen Zhang, Chris J. Myers, Chris Winstead, Hao Zheng:
Counterexample Generation for Infinite-State Chemical Reaction Networks. CoRR abs/2207.05207 (2022) - [i11]Md Rubel Ahmed, Bardia Nadimi, Hao Zheng:
Mining SoC Message Flows with Attention Model. CoRR abs/2209.07929 (2022) - 2021
- [i10]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System-on-Chip Designs. CoRR abs/2102.06989 (2021) - [i9]Md Rubel Ahmed, Hao Zheng:
Tools and Algorithms for SoC Communication Traces. CoRR abs/2103.10778 (2021) - 2020
- [i8]Hao Zheng, Yingying Zhang, Chris J. Myers:
Local State Space Analysis to Assist Partial Order Reduction. CoRR abs/2004.14971 (2020) - [i7]Hao Zheng, Andrew Price, Chris J. Myers:
Using Decision Diagrams to Compactly Represent the State Space for Explicit Model Checking. CoRR abs/2004.14995 (2020) - [i6]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. CoRR abs/2005.01574 (2020) - [i5]Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang:
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. CoRR abs/2005.02550 (2020) - [i4]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. CoRR abs/2005.11221 (2020) - 2019
- [i3]Thakur Neupane, Zhen Zhang, Curtis Madsen, Hao Zheng, Chris J. Myers:
Approximation Techniques for Stochastic Analysis of Biological Systems. CoRR abs/1901.07857 (2019) - [i2]Thakur Neupane, Chris J. Myers, Curtis Madsen, Hao Zheng, Zhen Zhang:
STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis. CoRR abs/1906.03978 (2019) - [i1]Yuting Cao, Hao Zheng, Sandip Ray:
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug. CoRR abs/1907.12901 (2019)
Coauthor Index
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