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ORCIDJohn V. McCanny
John Vincent McCanny
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- affiliation: Queen's University Belfast, UK
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Journal Articles
- 2011
[j28]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny:
QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. IEEE Trans. Signal Process. 59(4): 1858-1867 (2011)- 2010
- [j27]Liang Lu, John V. McCanny, Sakir Sezer:
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Comput. Digit. Tech. 4(5): 349-364 (2010) - [j26]Yingxi Lu, Máire O'Neill, John V. McCanny:
Evaluation of Random Delay Insertion against DPA on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(1): 11:1-11:20 (2010) - 2009
- [j25]Liang Lu, John V. McCanny, Sakir Sezer:
Subpixel Interpolation Architecture for Multistandard Video Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 19(12): 1897-1901 (2009) - 2008
- [j24]Yen-Kuang Chen
, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha:
Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. J. Signal Process. Syst. 51(3): 207-208 (2008) - [j23]Roger F. Woods, John V. McCanny, John G. McWhirter:
From Bit Level Systolic Arrays to HDTV Processor Chips. J. Signal Process. Syst. 53(1-2): 35-49 (2008) - 2006
- [j22]Neil Smyth, Máire McLoone, John V. McCanny:
WLAN security processor. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(7): 1506-1520 (2006) - [j21]Ciaran McIvor, Máire McLoone, John V. McCanny:
Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1946-1957 (2006) - 2005
- [j20]Zhaohui Liu, Kevin Dickson, John V. McCanny:
Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(4): 755-765 (2005) - 2004
- [j19]Shahid Masud, John V. McCanny:
Reusable silicon IP cores for discrete wavelet transform applications. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(6): 1114-1124 (2004) - [j18]Swee Yeow Yap, John V. McCanny:
A VLSI architecture for variable block size video motion estimation. IEEE Trans. Circuits Syst. II Express Briefs 51-II(7): 384-389 (2004) - 2003
- [j17]Zhaohui Liu, John V. McCanny, Gaye Lightbody, Richard L. Walke:
Generic SoC QR array processor for adaptive beamforming. IEEE Trans. Circuits Syst. II Express Briefs 50(4): 169-175 (2003) - [j16]Máire McLoone, John V. McCanny:
Rijndael FPGA Implementations Utilising Look-Up Tables. J. VLSI Signal Process. 34(3): 261-275 (2003) - 2001
- [j15]Shahid Masud, John V. McCanny:
Design of Silicon IP Cores for Biorthogonal Wavelet Transforms. J. VLSI Signal Process. 29(3): 179-196 (2001) - 2000
- [j14]Robert Hamill, John V. McCanny, Richard L. Walke:
Online CORDIC algorithm and VLSI architecture for implementing QR-array processors. IEEE Trans. Signal Process. 48(2): 592-598 (2000) - [j13]Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny:
Linear QR Architecture for a Single Chip Adaptive Beamformer. J. VLSI Signal Process. 24(1): 67-81 (2000) - 1999
- [j12]Tiong Jiu Ding, John V. McCanny, Yunsheng Hu:
Rapid design of application specific FFT cores. IEEE Trans. Signal Process. 47(5): 1371-1381 (1999) - 1997
- [j11]David W. Trainor, Roger F. Woods, John V. McCanny:
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". J. VLSI Signal Process. 16(1): 41-55 (1997) - 1996
- [j10]Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods:
A 64-point Fourier transform chip for video motion compensation using phase correlation. IEEE J. Solid State Circuits 31(11): 1751-1761 (1996) - 1995
- [j9]Stephen E. McQuillan, John V. McCanny:
A Systematic Methodology for the Design of High Performance Recursive Digital Filters. IEEE Trans. Computers 44(8): 971-982 (1995) - [j8]M. Yan, John V. McCanny, Yi Hu:
VLSI architectures for vector quantization. J. VLSI Signal Process. 10(1): 5-23 (1995) - 1994
- [j7]Stephen E. McQuillan, John V. McCanny:
Fast VLSI algorithms for division and square root. J. VLSI Signal Process. 8(2): 151-168 (1994) - 1992
- [j6]M. Yan, John V. McCanny:
Systolic inner product arrays with automatic word rounding. J. VLSI Signal Process. 4(2-3): 227-242 (1992) - [j5]Rajinder Jit Singh, John V. McCanny:
High performance VLSI architecture for Wave Digital Filtering. J. VLSI Signal Process. 4(4): 269-278 (1992) - 1990
- [j4]John V. McCanny, John G. McWhirter, Sun-Yuan Kung:
The use of data dependence graphs in the design of bit-level systolic arrays. IEEE Trans. Acoust. Speech Signal Process. 38(5): 787-793 (1990) - [j3]M. Yan, John V. McCanny:
A bit-level systolic architecture for implementing a VQ tree search. J. VLSI Signal Process. 2(3): 149-158 (1990) - 1989
- [j2]Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny:
Bit-Level systolic architectures for high performance IIR filtering. J. VLSI Signal Process. 1(1): 9-24 (1989) - 1987
- [j1]John V. McCanny, John G. McWhirter:
Some Systolic Array Developments in the United Kingdom. Computer 20(7): 51-63 (1987)
Conference and Workshop Papers
- 2017
- [c82]David Beckett, Sakir Sezer, John V. McCanny:
New sensing technique for detecting application layer DDoS attacks targeting back-end database resources. ICC 2017: 1-7 - 2012
- [c81]Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer:
Design of interlock-free combined allocators for Networks-on-Chip. SoCC 2012: 358-363 - 2011
- [c80]Ye Lu, John V. McCanny, Sakir Sezer:
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems. FPL 2011: 82-89 - [c79]Ye Lu, John V. McCanny, Sakir Sezer:
The Impact of Global Routing on the Performance of NoCs in FPGAs. ReConFig 2011: 369-374 - [c78]Ye Lu, John V. McCanny, Sakir Sezer:
Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. SoCC 2011: 302-307 - 2010
- [c77]Ye Lu, Sakir Sezer, John V. McCanny:
Advanced Multithreading Architecture with Hardware Based Scheduling. FPL 2010: 95-100 - [c76]Ye Lu, Sakir Sezer, John V. McCanny:
TLM2.0 based timing accurate modeling method for complex NoC systems. ISCAS 2010: 2900-2903 - [c75]Ye Lu, Sakir Sezer, John V. McCanny:
Design and analysis of an advanced static blocked multithreading architecture. SoCC 2010: 169-173 - [c74]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
High-Performance random data lookup for network processing. SoCC 2010: 272-277 - 2009
- [c73]Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh:
Is the differential frequency-based attack effective against random delay insertion? SiPS 2009: 051-056 - [c72]Yongping Liu, Sakir Sezer, John V. McCanny:
NFA decomposition and multiprocessing architecture for parallel regular expression processing. SoCC 2009: 347-350 - [c71]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
DDR3 based lookup circuit for high-performance network processing. SoCC 2009: 351-354 - 2008
- [c70]Yingxi Lu, Máire O'Neill, John V. McCanny:
FPGA implementation and analysis of random delay insertion countermeasure against DPA. FPT 2008: 201-208 - [c69]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny:
Modified givens rotations and their application to matrix inversion. ICASSP 2008: 1437-1440 - [c68]Yingxi Lu, Máire O'Neill, John V. McCanny:
Differential Power Analysis of a SHACAL-2 hardware implementation. ISCAS 2008: 2933-2936 - [c67]Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai:
Reduced-complexity MSGR-based matrix inversion. SiPS 2008: 124-128 - [c66]Liang Lu, John V. McCanny, Sakir Sezer:
Multi-standard sub-pixel interpolation architecture for video Motion Estimation. SoCC 2008: 229-232 - [c65]Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.:
High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374 - 2007
- [c64]Liang Lu, John V. McCanny, Sakir Sezer:
Systolic Array Based Architecture for Variable Block-Size Motion Estimation. AHS 2007: 160-168 - [c63]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
Novel Content Addressable Memory Architecture for Adaptive Systems. AHS 2007: 633-640 - [c62]Liang Lu, John V. McCanny, Sakir Sezer:
Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. ASAP 2007: 253-259 - [c61]John V. McCanny, Sakir Sezer, Máire O'Neill:
Exploring technology related design-space limitations of high performance network processing. ESSCIRC 2007: 222-231 - [c60]John V. McCanny:
From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems. DSP 2007: 16 - [c59]Liang Lu, John V. McCanny, Sakir Sezer:
Reconfigurable video motion estimation processor. SoCC 2007: 55-58 - [c58]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
A versatile content addressable memory architecture. SoCC 2007: 215-218 - 2006
- [c57]Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny:
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW 2006: 56 - [c56]John V. McCanny, Roger F. Woods, John G. McWhirter:
From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP 2006: 159-162 - [c55]Neil Smyth, Máire McLoone, John V. McCanny:
An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP 2006: 341-346 - [c54]Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny:
Design and analysis of matching circuit architectures for a closest match lookup. IPDPS 2006 - 2005
- [c53]Ciaran McIvor, Máire McLoone, John V. McCanny:
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT 2005: 13-18 - [c52]Zhaohui Liu, Kevin Dickson, John V. McCanny:
Hardware Design of Sphere Decoding for MIMO Systems. SoCC 2005: 287-290 - 2004
- [c51]Ciaran McIvor, Máire McLoone, John V. McCanny:
FPGA Montgomery Multiplier Architectures - A Comparison. FCCM 2004: 279-282 - [c50]Máire McLoone, Ciaran McIvor, John V. McCanny:
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. FPT 2004: 185-191 - [c49]Ciaran McIvor, Máire McLoone, John V. McCanny:
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) 2004: 509-512 - 2003
- [c48]Zhaohui Liu, Kevin Dickson, John V. McCanny:
A floating-point CORDIC based SVD processor. ASAP 2003: 194-203 - [c47]Swee Yeow Yap, John V. McCanny:
A VLSI Architecture for Advanced Video Coding Motion Estimation. ASAP 2003: 293- - [c46]Máire McLoone, John V. McCanny:
Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL 2003: 111-120 - [c45]Zhaohui Liu, John V. McCanny:
Implementation of adaptive beamforming based on QR decomposition for CDMA. ICASSP (2) 2003: 609-612 - [c44]Ciaran McIvor, Máire McLoone, John V. McCanny:
A high-speed, low latency RSA decryption silicon core. ISCAS (4) 2003: 133-136 - 2002
- [c43]Paul V. McCanny, John V. McCanny, Shahid Masud:
VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform. EUSIPCO 2002: 1-4 - [c42]Máire McLoone, John V. McCanny:
Efficient single-chip implementation of SHA-384 and SHA-512. FPT 2002: 311-314 - [c41]Paul V. McCanny, Shahid Masud, John V. McCanny:
Design and implementation of the symmetrically extended 2-D Wavelet Transform. ICASSP 2002: 3108-3111 - [c40]Kok Sing Yap, John V. McCanny:
A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems. ICASSP 2002: 4183 - [c39]Kok Sing Yap, John V. McCanny:
A mixed cost-function adaptive algorithm for ADSL time-domain equalization. ICC 2002: 1798-1802 - 2001
- [c38]Máire McLoone, John V. McCanny:
High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES 2001: 65-76 - [c37]Máire McLoone, John V. McCanny:
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL 2001: 152-161 - [c36]Zhaohui Liu, Gaye Lightbody, Richard L. Walke, Yi Hu, John V. McCanny:
Generic scheduling methods for a linear QR array SoC processor. ICASSP 2001: 1097-1100 - [c35]Paul V. McCanny, Shahid Masud, John V. McCanny:
An efficient architecture for the 2-D biorthogonal discrete wavelet transform. ICIP (3) 2001: 314-317 - 2000
- [c34]Shahid Masud, John V. McCanny:
Wavelet packet transforms for system-on-chip applications. ICASSP 2000: 3287-3290 - 1999
- [c33]Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny:
Novel mapping of a linear QR architecture. ICASSP 1999: 1933-1936 - [c32]Shahid Masud, John V. McCanny:
Rapid design of discrete orthonormal wavelet transforms using silicon IP components. ICASSP 1999: 2167-2170 - 1998
- [c31]Jill K. Hunter, John V. McCanny:
Rapid design of discrete transform cores. EUSIPCO 1998: 1-4 - [c30]Shahid Masud, John Vincent McCanny:
Finding a suitable wavelet for image compression applications. ICASSP 1998: 2581-2584 - [c29]Jill K. Hunter, John V. McCanny:
Discrete cosine transform generator for VLSI synthesis. ICASSP 1998: 2997-3000 - [c28]Shahid Masud, John V. McCanny:
Rapid Design of Discrete Orthonormal Wavelet Transforms. International Workshop on Rapid System Prototyping 1998: 142- - 1997
- [c27]John V. McCanny, Douglas Ridge, Yi Hu, Jill K. Hunter:
Hierarchical VHDL libraries for DSP ASIC design. ICASSP 1997: 675-678 - 1996
- [c26]Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods:
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP 1996: 83-92 - [c25]B. D. E. Smith, John V. McCanny:
Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel. ICECS 1996: 25-28 - [c24]Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods:
Error analysis of FFT architectures for digital video applications. ICECS 1996: 820-823 - 1994
- [c23]John V. McCanny, Yi Hu, M. Yan:
Automated design of DSP array processor chips. ASAP 1994: 33-44 - 1993
- [c22]Stephen E. McQuillan, John V. McCanny, Robert Hamill:
New algorithms and VLSI architectures for SRT division and square root. IEEE Symposium on Computer Arithmetic 1993: 80-86 - 1992
- [c21]Stephen E. McQuillan, John V. McCanny:
Algorithms and architectures for high performance recursive filtering. ASAP 1992: 230-244 - [c20]B. P. McGovern, Roger F. Woods, John V. McCanny:
The systematic design of high performance digital filters. ICASSP 1992: 609-612 - 1991
- [c19]Rajinder Jit Singh, John V. McCanny:
A wave digital filter three-port adaptor with fine grained pipelining. ASAP 1991: 116-128 - [c18]O. C. McNally, John V. McCanny, Roger F. Woods:
A 40 megasample IIR filter chip. ASAP 1991: 416-430 - [c17]John V. McCanny:
On the use of most significant digit first arithmetic in the design of high performance DSP chips. Algorithms and Parallel VLSI Architectures 1991: 243-260 - [c16]O. C. McNally, William P. Marnane, John V. McCanny:
Design and test of a bit parallel 2nd order IIR filter structure. ICASSP 1991: 1189-1192 - [c15]Stephen E. McQuillan, John V. McCanny:
A VLSI architecture for multiplication, division and square root. ICASSP 1991: 1205-1208 - [c14]O. C. McNally, John V. McCanny, Roger F. Woods:
Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI 1991: 19-28 - 1990
- [c13]Y. Hu, John V. McCanny, M. Yan:
Systolic VLSI compiler (SVC) for high performance vector quantisation chips. ASAP 1990: 145-155 - [c12]Rajinder Jit Singh, John V. McCanny:
Systolic two-port adaptor for high performance wave digital filtering. ASAP 1990: 379-388 - [c11]M. Yan, John V. McCanny, Yi Hu:
VLSI architectures for digital image coding. ICASSP 1990: 913-916 - [c10]Rajinder Jit Singh, John V. McCanny, Roger F. Woods:
Pipelined two-port adaptor for wave digital filtering. ICASSP 1990: 1033-1036 - [c9]O. C. McNally, John V. McCanny, Roger F. Woods:
Optimized bit level architectures for IIR filtering. ICCD 1990: 302-306 - 1989
- [c8]Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny:
A bit-level systolic architecture for very high performance IIR filters. ICASSP 1989: 2449-2452 - 1988
- [c7]Roger F. Woods, Simon C. Knowles, John V. McCanny, John G. McWhirter:
Systolic IIR filters with bit level pipelining. ICASSP 1988: 2072-2075 - [c6]S. M. F. Smyth, John V. McCanny, P. Challener:
An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation using music signals. ICASSP 1988: 2532-2535 - [c5]S. M. F. Smyth, John V. McCanny, P. Challener:
An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation. ICASSP 1988: 2544-2547 - 1987
- [c4]H. A. Kaouri, John V. McCanny:
Transformed sub-band coding of speech using vector quantization. ECST 1987: 2185-2188 - 1986
- [c3]J. C. White, John V. McCanny, A. McCabe, John G. McWhirter, R. Evans:
A high speed CMOS/SOS implementation of a bit level systolic correlator. ICASSP 1986: 1161-1164 - [c2]John V. McCanny:
Mapping system level functions on to bit level systolic arrays. ICASSP 1986: 2159-2162 - 1985
- [c1]J. S. Ward, John V. McCanny, John G. McWhirter:
A systolic implementation of the Winograd Fourier transform algorithm. ICASSP 1985: 1469-1472
Coauthor Index
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