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Journal Articles
- 2018
[j32]Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki:
Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2262-2270 (2018)- 2017
- [j31]Masayuki Arai, Kazuhiko Iwasaki:
Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1488-1495 (2017) - 2013
- [j30]Ryo Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints. IEICE Trans. Inf. Syst. 96-D(1): 141-145 (2013) - 2010
- [j29]Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki:
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. 93-D(1): 17-23 (2010) - [j28]Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Reduction of Area per Good Die for SoC Memory Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2463-2471 (2010) - 2009
- [j27]Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai:
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5(4): 520-528 (2009) - 2008
- [j26]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Study on Expansion of Convolutional Compactors over Galois Field. IEICE Trans. Inf. Syst. 91-D(3): 706-712 (2008) - [j25]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping. IEICE Trans. Inf. Syst. 91-D(3): 720-725 (2008) - [j24]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo:
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. IEICE Trans. Inf. Syst. 91-D(3): 726-735 (2008) - [j23]Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of Probabilistic Trapezoid Protocol for Data Replication. Inf. Media Technol. 3(3): 498-511 (2008) - [j22]Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of Probabilistic Trapezoid Protocol for Data Replication. J. Inf. Process. 16: 50-63 (2008) - [j21]Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa:
Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. J. Inf. Process. Syst. 4(4): 121-132 (2008) - 2006
- [j20]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery. Comput. Math. Appl. 51(2): 247-256 (2006) - [j19]Mamoru Ohara, Ryo Suzuki, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(9): 2386-2395 (2006) - 2005
- [j18]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1047-1054 (2005) - 2004
- [j17]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. IEICE Trans. Inf. Syst. 87-D(3): 586-591 (2004) - [j16]Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki:
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. 87-D(9): 2179-2185 (2004) - 2003
- [j15]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Seed Selection Procedure for LFSR-Based Random Pattern Generators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3063-3071 (2003) - [j14]Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara:
BIST-oriented test pattern generator for detection of transition faults. Syst. Comput. Jpn. 34(3): 76-84 (2003) - 2001
- [j13]Takeshi Asakawa, Kazuhiko Iwasaki:
Using ATPG vectors for BIST test pattern generator. Syst. Comput. Jpn. 32(11): 1-8 (2001) - 1996
- [j12]Kazuhiko Iwasaki, Shigeo Nakamura:
Aliasing Error for a Mask ROM Built-In Self-Test. IEEE Trans. Computers 45(3): 270-277 (1996) - 1995
- [j11]Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki:
On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers. IEEE Trans. Computers 44(11): 1265-1274 (1995) - 1994
- [j10]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato
, Mamoru Sugie:
A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability. IEEE Trans. Parallel Distributed Syst. 5(11): 1169-1184 (1994) - 1993
- [j9]Kazuhiko Iwasaki, Christian Iseli, Yuji Sato:
A uniform network for VLSI massively parallel computers. Syst. Comput. Jpn. 24(9): 22-31 (1993) - [j8]Masakatu Morii, Kazuhiko Iwasaki:
A Note on Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 42(9): 1152 (1993) - 1992
- [j7]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers. Parallel Comput. 18(10): 1079-1103 (1992) - 1990
- [j6]Kazuhiko Iwasaki:
Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing. Syst. Comput. Jpn. 21(5): 29-38 (1990) - [j5]Kazuhiko Iwasaki, Fumio Arakawa:
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 427-438 (1990) - 1989
- [j4]Kazuhiko Iwasaki, Tadahiko Nishimukai:
Aliasing Probabilities and Weight Distributions of Several Codes. Syst. Comput. Jpn. 20(9): 81-88 (1989) - 1988
- [j3]Kazuhiko Iwasaki:
Analysis and proposal of signature circuits for LSI testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 84-90 (1988) - 1987
- [j2]Kazuhiko Iwasaki, Tsuneo Funabashi, Tatsuaki Ueno:
Decoding method for shortened fire codes and its application to VLSI processor. Syst. Comput. Jpn. 18(1): 23-32 (1987) - 1986
- [j1]Kazuhiko Iwasaki, Noboru Yamaguchi, Yoshimune Hagiwara:
Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit. Syst. Comput. Jpn. 17(6): 20-30 (1986)
Conference and Workshop Papers
- 2017
- [c33]Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki:
Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation. ITC 2017: 1-8 - 2016
- [c32]Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki:
Critical-Area-Aware Test Pattern Generation and Reordering. ATS 2016: 191-196 - 2015
- [c31]Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki:
Note on Fast Bridge Fault Test Generation Based on Critical Area. ICA3PP (3) 2015: 729-740 - 2013
- [c30]Hongbo Shi, Kazuhiko Iwasaki:
Classification of DNS Queries for Anomaly Detection. PRDC 2013: 130-131 - 2012
- [c29]Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki:
Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage. Asian Test Symposium 2012: 89-94 - 2011
- [c28]Masayuki Arai, Kazuhiko Iwasaki:
Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors. PRDC 2011: 264-271 - 2010
- [c27]Takahiko Ikeda, Mamoru Ohara, Satoshi Fukumoto, Masayuki Arai, Kazuhiko Iwasaki:
A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments. PRDC 2010: 117-124 - 2009
- [c26]Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo:
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS 2009: 27-32 - 2008
- [c25]Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Hardware Overhead Reduction for Memory BIST. ITC 2008: 1 - 2006
- [c24]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Expansion of Convolutional Compactors over Galois Field. ATS 2006: 401-408 - [c23]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo:
Test Data Compression of 100x for Scan-Based BIST. ITC 2006: 1-10 - 2005
- [c22]Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of Probabilistic Trapezoid Protocol for Data Replication. DSN 2005: 782-791 - [c21]Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of error-masking and X-masking probabilities for convolutional compactors. ITC 2005: 10 - 2004
- [c20]Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki:
Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. Asian Test Symposium 2004: 190-195 - [c19]Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Finding a Recovery Line in Uncoordinated Checkpointing. ICDCS Workshops 2004: 628-633 - [c18]Masayuki Arai, Tabito Suzuki, Mamoru Ohara, Satoshi Fukumoto, Kazuhiko Iwasaki, Hee Yong Youn:
Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol. PRDC 2004: 143-150 - 2003
- [c17]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
A seed selection procedure for LFSR-based random pattern generators. ASP-DAC 2003: 869-874 - [c16]Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka:
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. Asian Test Symposium 2003: 28-31 - 2002
- [c15]Masayuki Arai, Hitoshi Kurosu, Mamoru Ohara, Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki:
Experiment for High-Assurance Video Conference System over the Internet. HASE 2002: 137-142 - [c14]Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki:
Adaptive Checkpointing for Time Warp Technique with a Limited Number of Checkpoints. ICDCS Workshops 2002: 95-100 - [c13]Masayuki Arai, Hitoshi Kurosu, Satoshi Fukumoto, Kazuhiko Iwasaki:
Evaluation of Convolutional-Code-Based FEC under Limited Recovery Time and Its Application to Real-time Transmission. PRDC 2002: 239-246 - 2001
- [c12]Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara:
Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium 2001: 379-384 - [c11]Masayuki Arai, Anna Yamamoto, Anna Yamaguchi, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of Using Convolutional Codes to Recover Packet Losses over Burst Erasure Channels. PRDC 2001: 258-265 - 2000
- [c10]Masayuki Arai, Anna Yamaguchi, Kazuhiko Iwasaki:
Method to Recover Internet Packet Losses Using (n, n - 1, m) Convolutional Codes. DSN 2000: 382-389 - [c9]Anna Yamaguchi, Masayuki Arai, Kazuhiko Iwasaki:
Evaluation of multicast error recovery using convolutional codes. PRDC 2000: 37-44 - 1999
- [c8]Masayuki Arai, Atsushi Chiba, Kazuhiko Iwasaki:
Measurement and Modeling of Burst Packet Losses in Internet End-to-End Communications. PRDC 1999: 260-267 - 1997
- [c7]Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki:
Experimental fault analysis of 1 Mb SRAM chips. VTS 1997: 31-36 - 1994
- [c6]Kazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura:
Aliasing error for a mask ROM built-in self-test. VTS 1994: 93-98 - 1993
- [c5]Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki:
On the maximum value of aliasing probabilities for single input signature registers. VTS 1993: 267-274 - 1992
- [c4]Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami:
A defect-tolerant design for mask ROMs. VTS 1992: 171-175 - 1991
- [c3]Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. ITC 1991: 758-767 - 1990
- [c2]Kazuhiko Iwasaki, Noboru Yamaguchi:
Design of signature circuits based on weight distributions of error-correcting codes. ITC 1990: 779-785 - 1988
- [c1]Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada:
Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. ICCD 1988: 102-105
Coauthor Index
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